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authorJonathan Zhang <jonzhang@fb.com>2020-09-03 14:31:37 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:36:34 +0000
commit5bb89e7f0c7e08142cd05dd176b459771d81b8e1 (patch)
tree498e32c52f63c8ef56f9d461c97878520b3bb56b
parent27dd66aca7613e3851a1b7a2826272c9c50e1697 (diff)
downloadcoreboot-5bb89e7f0c7e08142cd05dd176b459771d81b8e1.tar.xz
vendorcode/intel/FSP2_0/CPX-SP: update to ww36
Intel CPX-SP FSP ww36 release has following changes: * Update FSP header version to change among FSP releases. * Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11 (OEM strings) generation. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h16
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h3
2 files changed, 11 insertions, 8 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
index 02bab70e7c..d892c9a8a9 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
@@ -370,16 +370,18 @@ typedef struct {
**/
UINT32 mmiohBase;
-/** Offset 0x0098 - High Gap
+/** Offset 0x0098 - CPU Physical Address Limit
+ CPU Physical Address Limit
+ 0:Disable, 1:Enable
+**/
+ UINT8 CpuPaLimit;
+
+/** Offset 0x0099 - High Gap
Enable or Disable High Gap
$EN_DIS
**/
UINT8 highGap;
-/** Offset 0x0099
-**/
- UINT8 UnusedUpdSpace0;
-
/** Offset 0x009A - MMIO High Size
MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
per CPU. Range 1-1024
@@ -400,7 +402,7 @@ typedef struct {
/** Offset 0x009E
**/
- UINT8 UnusedUpdSpace1[2];
+ UINT8 UnusedUpdSpace0[2];
/** Offset 0x00A0 - } TYPE:{Combo
Enable or Disable
@@ -723,7 +725,7 @@ typedef struct {
/** Offset 0x015C
**/
- UINT8 UnusedUpdSpace2[2];
+ UINT8 UnusedUpdSpace1[2];
/** Offset 0x015E
**/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 0f5b33fe52..db39c3be3c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -45,6 +45,7 @@ are permitted provided that the following conditions are met:
#define MAX_IMC 2
#define MAX_CH 6
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC)
+#define MAX_CHA_MAP 4
// Maximum KTI PORTS to be used in structure definition
#if (MAX_SOCKET == 1)
@@ -154,7 +155,7 @@ typedef struct {
uint16_t M2PciePresentBitmap;
uint8_t TotM3Kti;
uint8_t TotCha;
- uint32_t ChaList;
+ uint32_t ChaList[MAX_CHA_MAP];
uint32_t SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;