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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-06-19 15:41:49 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-06-19 15:41:49 +0000 |
| commit | 6114311c8eaabd14f524e2884316249de9d9578b (patch) | |
| tree | e879c7ca522eaa950876be784982c18fbe12e727 | |
| parent | 62cfe169fafa5bd6a37a71cde221fc09e0b47f0e (diff) | |
| download | coreboot-6114311c8eaabd14f524e2884316249de9d9578b.tar.xz | |
Convert the MSI MS-6178 board to CBFS.
Also, enable HIGH_TABLES support for this board.
The HIGH_TABLES failed with:
No matching ram area found for range:
[0x00000000000f0000, 0x0000000000100000)
Ram areas
[0x0000000000000000, 0x0000000000001000) Reserved
[0x0000000000001000, 0x00000000000a0000) RAM
[0x0000000000100000, 0x000000000fff0000) RAM
[0x000000000fff0000, 0x0000000010000000) Reserved
SELFBOOT RETURNED!
Boot failed.
The fix was to change northbridge.c as follows:
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ ram_resource(dev, idx++, 768, tolmk - 768);
This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/msi/ms6178/Options.lb | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/i82810/northbridge.c | 2 | ||||
| -rw-r--r-- | targets/msi/ms6178/Config.lb | 4 |
3 files changed, 8 insertions, 9 deletions
diff --git a/src/mainboard/msi/ms6178/Options.lb b/src/mainboard/msi/ms6178/Options.lb index 07c1a10770..8ccd8683e1 100644 --- a/src/mainboard/msi/ms6178/Options.lb +++ b/src/mainboard/msi/ms6178/Options.lb @@ -65,6 +65,7 @@ uses CONFIG_UDELAY_TSC uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN +uses HAVE_HIGH_TABLES default ROM_SIZE = 512 * 1024 default HAVE_FALLBACK_BOOT = 1 @@ -75,7 +76,7 @@ default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. default ROM_IMAGE_SIZE = 64 * 1024 -default FALLBACK_SIZE = 128 * 1024 +default FALLBACK_SIZE = ROM_IMAGE_SIZE default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 16 * 1024 default HAVE_OPTION_TABLE = 0 @@ -96,10 +97,6 @@ default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_CONSOLE_VGA = 1 default CONFIG_PCI_ROM_RUN = 1 - -# -# CBFS -# -# -default CONFIG_CBFS=0 +default CONFIG_CBFS = 1 +default HAVE_HIGH_TABLES = 1 end diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index bfbd338069..40c8ee0e69 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -170,7 +170,7 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 768, tolmk - 768); #if HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ diff --git a/targets/msi/ms6178/Config.lb b/targets/msi/ms6178/Config.lb index 6c5f058827..1276c88a77 100644 --- a/targets/msi/ms6178/Config.lb +++ b/targets/msi/ms6178/Config.lb @@ -22,7 +22,6 @@ target ms6178 mainboard msi/ms6178 option ROM_SIZE = 512 * 1024 -# option ROM_SIZE = (512 * 1024) - (32 * 1024) option MAINBOARD_VENDOR = "MSI" option MAINBOARD_PART_NUMBER = "MS-6178" @@ -48,3 +47,6 @@ romimage "fallback" end buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" + +# pci_rom i810.vga vendor_id=0x8086 device_id=0x7120 + |