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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-29 09:40:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2019-01-06 13:19:05 +0000
commit63649d24fd616dad397a4ae18f9aede43c6ce2dc (patch)
treedf6c66c50a330d79d81c315f43547f0fdc45978e
parenta144e4d6fa93b9ba129b3aa8991cc5fb2ec3c8a6 (diff)
downloadcoreboot-63649d24fd616dad397a4ae18f9aede43c6ce2dc.tar.xz
usbdebug: Refactor init calls
Expose the function that can unconditionally re-initialise EHCI debug host and gadget. Given the missing header in soc/intel files that prevented building with USBDEBUG_IN_ROMSTAGE=y, it is not actually known if those SOCs work at all for usbdebug. Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/drivers/usb/ehci_debug.c21
-rw-r--r--src/include/console/usb.h1
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c5
-rw-r--r--src/soc/intel/fsp_baytrail/romstage/romstage.c6
-rw-r--r--src/soc/intel/fsp_broadwell_de/romstage/romstage.c6
-rw-r--r--src/southbridge/intel/fsp_rangeley/romstage.c6
6 files changed, 24 insertions, 21 deletions
diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index 52b4bdde6b..fdd2c72785 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -648,11 +648,19 @@ void usbdebug_disable(void)
#endif
-static int usbdebug_hw_init(void)
+int usbdebug_hw_init(bool force)
{
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
unsigned int ehci_base, dbg_offset;
+ if (dbgp_enabled() && !force)
+ return 0;
+
+ /* Do not attempt slow gadget init in postcar. */
+ if (ENV_POSTCAR)
+ return -1;
+
+ /* Do full init if state claims we are still not enabled. */
if (ehci_debug_hw_enable(&ehci_base, &dbg_offset))
return -1;
return usbdebug_init_(ehci_base, dbg_offset, dbg_info);
@@ -682,12 +690,7 @@ static void migrate_ehci_debug(int is_recovery)
car_set_var(glob_dbg_info_p, dbg_info_cbmem);
}
- /* Redo full init in ramstage if state claims we
- * are still not enabled. Should never happen. */
- rv = dbgp_enabled() ? 0 : -1;
- if (!ENV_POSTCAR && rv < 0)
- rv = usbdebug_hw_init();
-
+ rv = usbdebug_hw_init(false);
if (rv < 0)
printk(BIOS_DEBUG, "usbdebug: Failed hardware init\n");
else
@@ -720,11 +723,11 @@ void usbdebug_init(void)
* from CBMEM.
*/
if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_ROMSTAGE)
- usbdebug_hw_init();
+ usbdebug_hw_init(false);
/* USB console init is done early in ramstage if it was
* not done in romstage, this does not require CBMEM.
*/
if (!IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) && ENV_RAMSTAGE)
- usbdebug_hw_init();
+ usbdebug_hw_init(false);
}
diff --git a/src/include/console/usb.h b/src/include/console/usb.h
index 78956d7936..45a501d536 100644
--- a/src/include/console/usb.h
+++ b/src/include/console/usb.h
@@ -21,6 +21,7 @@
#include <stdint.h>
void usbdebug_init(void);
+int usbdebug_hw_init(bool force);
void usb_tx_byte(int idx, unsigned char data);
void usb_tx_flush(int idx);
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 1975051207..44a1f3e714 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -238,10 +238,9 @@ void sdram_initialize(struct pei_data *pei_data)
die("UEFI PEI System Agent not found.\n");
}
-#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* mrc.bin reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif
+ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE))
+ usbdebug_hw_init(true);
/* For reference print the System Agent version
* after executing the UEFI PEI stage.
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index bc49a418f4..15ab9ec949 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -20,6 +20,7 @@
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <console/console.h>
+#include <console/usb.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
@@ -225,10 +226,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
-#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
+ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE))
+ usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 801f9e0e5e..924aab2a25 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -21,6 +21,7 @@
#include <arch/cbfs.h>
#include <cbmem.h>
#include <console/console.h>
+#include <console/usb.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
#include <romstage_handoff.h>
@@ -101,10 +102,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
-#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
+ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE))
+ usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index f986d79d36..bf92049479 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -24,6 +24,7 @@
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <console/console.h>
+#include <console/usb.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <program_loading.h>
#include <northbridge/intel/fsp_rangeley/northbridge.h>
@@ -99,10 +100,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
-#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
- usbdebug_init();
-#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
+ if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE))
+ usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);