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authorLijian Zhao <lijian.zhao@intel.com>2017-08-29 17:26:48 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-06 16:53:37 +0000
commit6d7063c2ac562cab72e9556102da87c61be32d3f (patch)
tree244417a2e87f150bf04d32e0b1c0de5220fc87a4
parent8688536ca201c7dfa77b570036c5759ff998df91 (diff)
downloadcoreboot-6d7063c2ac562cab72e9556102da87c61be32d3f.tar.xz
soc/intel/cannonlake: Add Vboot/ChromeOS support
Add Vboot and ChromeOS support in SOC Kconfig, include a separated verstage in Makefiles.inc as well. Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/cannonlake/Kconfig11
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc2
2 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f72c2b302a..9525ab488d 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -123,4 +123,15 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
+config CHROMEOS
+ select CHROMEOS_RAMOOPS_DYNAMIC
+
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_OPROM_MATTERS
+ select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+ select VBOOT_STARTS_IN_BOOTBLOCK
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
endif
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index dba04a85fa..d3fd5f2e8c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -45,7 +45,9 @@ postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c
+verstage-y += pmutil.c
verstage-y += spi.c
+verstage-$(CONFIG_UART_DEBUG) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake