drivers/spi: provide optional implementation of boot_device_rw()

On many x86 platforms the boot device is SPI which is memory
mapped. However, in order to write to the boot device one needs
to use the SPI api. Therefore, provide a common implementation
of boot_device_rw() which has no mmap() functionality. It only
reads, writes, and erases. This will be used in the existing
infrastructure but in a SPI agnostic way.

Two options are added:
1. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
2. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY

The former is auto-selected when COMMON_CBFS_SPI_WRAPPER is not
selected. The latter can be used to include the implementation
in the early stages such as bootblock, verstage, and romstage.

BUG=chrome-os-partner:56151

Change-Id: I2aa75f88409309e3f9b9bd79b52d27c0061139c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16200
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 112 insertions, 0 deletions

diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index 5eb9b56557..4c2fd1f060 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -39,6 +39,23 @@ config BOOT_DEVICE_SPI_FLASH_BUS
 	help
 	  Which SPI bus the boot device is connected to.
 
+config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
+	bool
+	default y if !COMMON_CBFS_SPI_WRAPPER
+	default n
+	depends on BOOT_DEVICE_SPI_FLASH
+	help
+	  Provide common implementation of the RW boot device that
+	  doesn't provide mmap() operations.
+
+config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
+	bool
+	default n
+	depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
+	help
+	  Include the common implementation in all stages, including the
+	  early ones.
+
 config SPI_FLASH_INCLUDE_ALL_DRIVERS
 	bool
 	default n if COMMON_CBFS_SPI_WRAPPER
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
index 8fd59846dc..92baf62bc3 100644
--- a/src/drivers/spi/Makefile.inc
+++ b/src/drivers/spi/Makefile.inc
@@ -9,6 +9,7 @@ endif
 
 bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
 bootblock-$(CONFIG_SPI_FLASH) += spi_flash.c
+bootblock-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c
 bootblock-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c
 bootblock-$(CONFIG_SPI_FLASH_AMIC) += amic.c
 bootblock-$(CONFIG_SPI_FLASH_ATMEL) += atmel.c
@@ -23,6 +24,7 @@ bootblock-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
 
 romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
 romstage-$(CONFIG_SPI_FLASH) += spi_flash.c
+romstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c
 romstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c
 romstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c
 romstage-$(CONFIG_SPI_FLASH_ATMEL) += atmel.c
@@ -37,6 +39,7 @@ romstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
 
 verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
 verstage-$(CONFIG_SPI_FLASH) += spi_flash.c
+verstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c
 verstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c
 verstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c
 verstage-$(CONFIG_SPI_FLASH_ATMEL) += atmel.c
@@ -51,6 +54,7 @@ verstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
 
 ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
 ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c
+ramstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP) += boot_device_rw_nommap.c
 ramstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c
 ramstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c
 ramstage-$(CONFIG_SPI_FLASH_ATMEL) += atmel.c
@@ -66,6 +70,7 @@ ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
 ifeq ($(CONFIG_SPI_FLASH_SMM),y)
 # SPI flash driver interface
 smm-$(CONFIG_SPI_FLASH) += spi_flash.c
+smm-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP) += boot_device_rw_nommap.c
 
 # drivers
 smm-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c
diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c
new file mode 100644
index 0000000000..2a9f19f1f8
--- /dev/null
+++ b/src/drivers/spi/boot_device_rw_nommap.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <boot_device.h>
+#include <spi_flash.h>
+
+static struct spi_flash *sfg CAR_GLOBAL;
+
+static ssize_t spi_readat(const struct region_device *rd, void *b,
+				size_t offset, size_t size)
+{
+	struct spi_flash *sf = car_get_var(sfg);
+
+	if (sf == NULL)
+		return -1;
+
+	if (sf->read(sf, offset, size, b))
+		return -1;
+
+	return size;
+}
+
+static ssize_t spi_writeat(const struct region_device *rd, const void *b,
+				size_t offset, size_t size)
+{
+	struct spi_flash *sf = car_get_var(sfg);
+
+	if (sf == NULL)
+		return -1;
+
+	if (sf->write(sf, offset, size, b))
+		return -1;
+
+	return size;
+}
+
+static ssize_t spi_eraseat(const struct region_device *rd,
+				size_t offset, size_t size)
+{
+	struct spi_flash *sf = car_get_var(sfg);
+
+	if (sf == NULL)
+		return -1;
+
+	if (sf->erase(sf, offset, size))
+		return -1;
+
+	return size;
+}
+
+static const struct region_device_ops spi_ops = {
+	.readat = spi_readat,
+	.writeat = spi_writeat,
+	.eraseat = spi_eraseat,
+};
+
+static const struct region_device spi_rw =
+	REGION_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE);
+
+void boot_device_init(void)
+{
+	const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
+	const int cs = 0;
+
+	if (car_get_var(sfg) != NULL)
+		return;
+
+	car_set_var(sfg, spi_flash_probe(bus, cs));
+}
+
+const struct region_device *boot_device_rw(void)
+{
+	if (car_get_var(sfg) == NULL)
+		return NULL;
+
+	return &spi_rw;
+}