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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-10 16:33:21 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-14 17:16:31 +0000 |
| commit | 7465b9dc8d9073681b5a2b8ec3ab687156f1bc2b (patch) | |
| tree | 457a0421f6517d01019d447ccfc1fafd02feac69 | |
| parent | cbdf9762d7d2d0702b6672585087b4f98c18d265 (diff) | |
| download | coreboot-7465b9dc8d9073681b5a2b8ec3ab687156f1bc2b.tar.xz | |
amd/stoneyridge: Define bits for AcpiConfig
Add defintions for PMx74.
Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 771554a40e..c79457b4c7 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -73,6 +73,19 @@ #define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 +#define PM_ACPI_DECODE_STD BIT(0) +#define PM_ACPI_GLOBAL_EN BIT(1) +#define PM_ACPI_RTC_EN_EN BIT(2) +#define PM_ACPI_TIMER_EN_EN BIT(4) +#define PM_ACPI_MASK_ARB_DIS BIT(6) +#define PM_ACPI_BIOS_RLS BIT(7) +#define PM_ACPI_PWRBTNEN_EN BIT(8) +#define PM_ACPI_REDUCED_HW_EN BIT(9) +#define PM_ACPI_BLOCK_PCIE_PME BIT(24) +#define PM_ACPI_PCIE_WAK_MASK BIT(25) +#define PM_ACPI_WAKE_AS_GEVENT BIT(27) +#define PM_ACPI_NB_PME_GEVENT BIT(28) +#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) #define PM_PMIO_DEBUG 0xd2 |