diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2018-01-16 14:40:10 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-22 21:43:34 +0000 |
| commit | 7ea8e02f4b948c0a59648d59a0ffe53d1be40cd3 (patch) | |
| tree | 631ac0cc2480633085a9db27bf09bebb7e10368b | |
| parent | a318d2812dd2af2087557cd2a8172b38bfc589e9 (diff) | |
| download | coreboot-7ea8e02f4b948c0a59648d59a0ffe53d1be40cd3.tar.xz | |
amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbers
CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 14 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 14 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 675e071ba9..7f1e210123 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -287,20 +287,6 @@ #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 -static inline int sb_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 2); -} - -static inline int sb_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 3); -} - void sb_enable_rom(void); void configure_stoneyridge_uart(void); void sb_clk_output_48Mhz(void); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index cf896cb857..0af774bbf6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -38,6 +38,20 @@ static int is_sata_config(void) || (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde)); } +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) || + (CONFIG_STONEYRIDGE_SATA_MODE == SataAhci); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) || + (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); +} + void SetFchResetParams(FCH_RESET_INTERFACE *params) { params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); |