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| author | Subrata Banik <subrata.banik@intel.com> | 2017-05-19 14:02:11 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-01 21:50:08 +0200 |
| commit | 8274f988d918fa9e1c2ecd45a8c912e75feca1c6 (patch) | |
| tree | 881fce2d1e0c2665f8a1246351b1f95ff4774d0c | |
| parent | d18b53f45dca75d82bc011e217edad045add23ef (diff) | |
| download | coreboot-8274f988d918fa9e1c2ecd45a8c912e75feca1c6.tar.xz | |
src/include/device: Add System Agent (SA) device ids
Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/include/device/pci_ids.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 541e041e85..bd9b2d5e35 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2815,8 +2815,17 @@ #define PCI_DEVICE_ID_INTEL_GLK_IGD 0x3184 /* Intel Northbridge Ids */ -#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 -#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 +#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 +#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 +#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 +#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c +#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 +#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c +#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 +#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 |