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authorJohn Zhao <john.zhao@intel.com>2020-06-03 13:06:24 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-09 18:43:57 +0000
commit92a3a304af8b97d5628646788263c7ddf2b3a998 (patch)
treec0ccee14cc0c8e23ae23ddfefae67e2fa4045bf8
parent6d81eceb74c3821b7a9e0aadda63c7231a3c9caf (diff)
downloadcoreboot-92a3a304af8b97d5628646788263c7ddf2b3a998.tar.xz
soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs
The Connect Topology Command(CNTP) is sent with default timeout value (0x1388) along with FW CM. The CNTP is supposed to be skipped while using SW CM. While transition from FW CM to SW CM, the default timeout value could cause boot time delay up to ~10 seconds. Set this FSPS UPD ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs value. While FSP finds this UPD value being 0, FSP will skip sending CNTP. BUG=b:155893566 TEST=Built image with SW CM Thunderbolt firmware and verified no outstanding delay time while using FSP v3197 during boot to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/chip.h3
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c7
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index ed09aaa936..e69369981d 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -238,6 +238,9 @@ struct soc_intel_tigerlake_config {
*/
uint16_t TcssAuxOri;
+ /* Connect Topology Command timeout value */
+ uint16_t ITbtConnectTopologyTimeoutInMs;
+
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index bdcd357173..926d8eb7b4 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -114,6 +114,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < 8; i++)
params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i];
+ /*
+ * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
+ * evaluate this UPD value and skip sending command. There will be no
+ * delay for command completion.
+ */
+ params->ITbtConnectTopologyTimeoutInMs = 0;
+
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
params->PchLockDownGlobalSmi = 0;