diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 22:50:08 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 13:03:51 +0000 |
| commit | a82f06cb8fd5899a37b6b73ec682e8058f42a93e (patch) | |
| tree | 201955714cd32385223b17423122736f714daebc | |
| parent | e15dc9eb1e4aa8ae87e398fb0d6eb895f4bb86d5 (diff) | |
| download | coreboot-a82f06cb8fd5899a37b6b73ec682e8058f42a93e.tar.xz | |
sb/intel/lynxpoint/acpi: Split USB into EHCI and xHCI
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/ehci.asl | 34 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/xhci.asl (renamed from src/southbridge/intel/lynxpoint/acpi/usb.asl) | 33 |
3 files changed, 39 insertions, 35 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/ehci.asl b/src/southbridge/intel/lynxpoint/acpi/ehci.asl new file mode 100644 index 0000000000..2a54304a2c --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/ehci.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// EHCI Controller 0:1d.0 + +Device (EHCI) +{ + Name (_ADR, 0x001d0000) + + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) + + // Leave USB ports on for to allow Wake from USB + + Method (_S3D, 0) // Highest D State in S3 State + { + Return (2) + } + + Method (_S4D, 0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0) + + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index e683c752ce..40d206d3dd 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -67,8 +67,11 @@ Scope (\) // PCI Express Ports 0:1c.x #include <southbridge/intel/common/acpi/pcie.asl> -// USB 0:1d.0 and 0:1a.0 -#include "usb.asl" +// USB EHCI 0:1d.0 and 0:1a.0 +#include "ehci.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl" // LPC Bridge 0:1f.0 #include "lpc.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index fbb7090819..65f1869e10 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -1,38 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// EHCI Controller 0:1d.0 - -Device (EHCI) -{ - Name (_ADR, 0x001d0000) - - Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) - - // Leave USB ports on for to allow Wake from USB - - Method (_S3D, 0) // Highest D State in S3 State - { - Return (2) - } - - Method (_S4D, 0) // Highest D State in S4 State - { - Return (2) - } - - Device (HUB7) - { - Name (_ADR, 0) - - Device (PRT1) { Name (_ADR, 1) } // USB Port 0 - Device (PRT2) { Name (_ADR, 2) } // USB Port 1 - Device (PRT3) { Name (_ADR, 3) } // USB Port 2 - Device (PRT4) { Name (_ADR, 4) } // USB Port 3 - Device (PRT5) { Name (_ADR, 5) } // USB Port 4 - Device (PRT6) { Name (_ADR, 6) } // USB Port 5 - } -} - // XHCI Controller 0:14.0 Device (XHCI) |