summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-09-15 00:41:14 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-22 17:36:42 +0000
commitaaea66aca89ae396b0067f63bb11bba208af3da9 (patch)
tree6d3d690589ba6a92b2ee9062228bc6806af5ab35
parentd071c4d3c3b9cefff715783fb4485110f08cd51b (diff)
downloadcoreboot-aaea66aca89ae396b0067f63bb11bba208af3da9.tar.xz
nb/intel/ironlake: Use `MSAC` definition
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7632 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/northbridge/intel/ironlake/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 0cefe4f888..68eefec9dd 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3654,8 +3654,8 @@ void chipset_init(const int s3resume)
MCHBAR16_OR(0x2c30, 0x200);
MCHBAR16(0x2c32) = 0x434;
MCHBAR32_AND_OR(0x2c44, 0, 0x1053687);
- pci_read_config8(GMA, 0x62); // = 0x2
- pci_write_config8(GMA, 0x62, 0x2);
+ pci_read_config8(GMA, MSAC); // = 0x2
+ pci_write_config8(GMA, MSAC, 0x2);
read8(DEFAULT_RCBA + 0x2318);
write8(DEFAULT_RCBA + 0x2318, 0x47);
read8(DEFAULT_RCBA + 0x2320);