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| author | Hannah Williams <hannah.williams@intel.com> | 2015-08-23 17:24:43 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:38:57 +0100 |
| commit | b0eb594b34f17ccb357c768f38d0716679e93e7f (patch) | |
| tree | 20c6ce5a301ad186e05ff1d204315576decc09ce | |
| parent | 103f00daaba07c0bf6688642cbe658873dc5a0a8 (diff) | |
| download | coreboot-b0eb594b34f17ccb357c768f38d0716679e93e7f.tar.xz | |
soc/braswell: Set max frequency to be turbo frequency
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using
ratio from MSR_IACORE_TURBO_RATIOS
Also, punit_init needs to be called before enabling this frequency.
Original-Reviewed-on: https://chromium-review.googlesource.com/295268
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/tsc_freq.c | 9 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1e085d7e93..155c8a2e46 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Perform silicon specific init. */ intel_silicon_init(); + set_max_freq(); set_board_id(); /* Get GPIO initial states from mainboard */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index fff882eb9b..f4f1a8be8c 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -72,18 +72,23 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* Enable Burst Mode */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; /* * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); + msr = rdmsr(MSR_IACORE_TURBO_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; |