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| author | Werner Zeh <werner.zeh@siemens.com> | 2015-02-10 10:16:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-05 12:45:10 +0100 |
| commit | b5a374d58befa96f718d0c2cee9afafb60867f18 (patch) | |
| tree | 6be19a296a2155b51933901d83cdd3d2025a6654 | |
| parent | fb9d4caf160436a9f9b16f2103cf635da8460685 (diff) | |
| download | coreboot-b5a374d58befa96f718d0c2cee9afafb60867f18.tar.xz | |
fsp_baytrail: Add new microcode for Bay Trail M
Add a new microcode for Bay Trail M D0 stepping used
in cpu N2807 silicon.
In addition, a selection of the used CPU type has
been added (I or M/D) which allows to use only the
really needed microcode for a given CPU type.
Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/soc/intel/fsp_baytrail/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 |
3 files changed, 21 insertions, 9 deletions
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 87839c40b4..d97879fc5d 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -50,6 +50,10 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select ROMSTAGE_RTC_INIT +config SOC_INTEL_FSP_BAYTRAIL_MD + bool + default n + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 57aae34349..ec633272c2 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,20 +19,24 @@ unsigned microcode[] = { -/* + /* * The problem is that these microcode files are not in the tree. They come * with FSP, so let the user deal with the include paths when HAVE_FSP_BIN * is enabled. */ #if IS_ENABLED(CONFIG_HAVE_FSP_BIN) +#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ + #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1 + #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3 + #include "M0130679901.h" // M0130679: Bay Trail I D0 +#else + /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ + #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping +#endif /* CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD */ +#endif /* CONFIG_HAVE_FSP_BIN */ -/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ -#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 -#include "M0130679901.h" // M0130679: Baytrail I D0 - -#endif - /* Dummy terminator */ + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec553146af..2af22016cb 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if !IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x30000 +#else + #define MICROCODE_REGION_LENGTH 0x10000 +#endif |