some todo and comment for ron.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 21 insertions, 12 deletions

diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index f4c3344612..b3a9b839ee 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -104,13 +104,17 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #include "cpu/amd/model_gx2/syspreinit.c"
 static void msr_init(void)
 {
+	/* total physical memory */
 	__builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
 
+	/* traditional memory 0kB-512kB, 512kB-1MB */
 	__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
 
         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
+
+	/* put code in northbridge[init].c here */
 }
 
 
@@ -121,7 +125,7 @@ static void main(unsigned long bist)
 	};
 
 	SystemPreInit();
-	msr_init();
+	
 
 	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 	uart_init();
@@ -136,6 +140,8 @@ static void main(unsigned long bist)
 	
 	sdram_initialize(1, memctrl);
 
+	msr_init();
+
 	/* Check all of memory */
 	//ram_check(0x00000000, 640*1024);
 }
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 6f638c244e..0998a6af96 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -330,16 +330,13 @@ static void GLPCIInit(void){
 	/* */
 	/*  R1 - GLPCI settings for SysMem space.*/
 	/* */
-	
 	/*  Get systop from GLIU0 SYSTOP Descriptor*/
-
 	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
 			break;
 		}
 	}
-
 	if (gl) {
 		msrnum = gl->desc_name;
 		msr = rdmsr(msrnum);
@@ -373,16 +370,12 @@ static void GLPCIInit(void){
 	msrnum = CPU_RCONF_A0_BF;
 	wrmsr(msrnum, msr);
 
-
 	msrnum = CPU_RCONF_C0_DF;
 	wrmsr(msrnum, msr);
 
-
 	msrnum = CPU_RCONF_E0_FF;
 	wrmsr(msrnum, msr);
 
-
-
 	/*  Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
 	msrnum = GLPCI_A0_BF;
 	msr.hi =  0x35353535;
@@ -400,7 +393,6 @@ static void GLPCIInit(void){
 	wrmsr(msrnum, msr);
 
 	/*  Set WSREQ*/
-
 	msrnum = CPU_DM_CONFIG0;
 	msr = rdmsr(msrnum);
 	msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index 99cc5d28c5..eb8f9f5140 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -156,12 +156,23 @@ static void dummy(void)
 }
 
 /* see page 412 of the cs5536 companion book */
-static int cs5536_setup_onchipuart(void) {
+static int cs5536_setup_onchipuart(void)
+{
+	/* ToDo:
+	 * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
+	 *    GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
+	 * 2. Enable UART IO space in MDD
+	 *    MSR 0x51400014 bit 18:16
+	 * 3. Enable UART controller
+	 *    MSR 0x5140003A bit 0, 1
+	 * 4. IRQ routing on IRQ Mapper
+	 *    MSR 0x51400021 bit [27:24]
+	 */
 	msr_t msr;
 	msr.lo = 2;
 	msr.hi = 0;
-	wrmsr(0x5160003a, msr);
-	wrmsr(0x5160003e, msr);
+	wrmsr(0x5140003a, msr);
+	wrmsr(0x5140003e, msr);
 }
 
 static int cs5536_early_setup(void)