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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-08-10 20:37:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-08-11 19:10:08 +0000 |
| commit | c0d4eeb387f9892ad33e117ab3fc3648918e823a (patch) | |
| tree | 50ecdbd478abc8e93d7eca5c0b8a4ef553040e57 | |
| parent | 4bf419fbf750eb4c3f3f7f05486ea4bf503274ed (diff) | |
| download | coreboot-c0d4eeb387f9892ad33e117ab3fc3648918e823a.tar.xz | |
soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
When address and data register for the SIO control register access is
passed as one I/O region with a size of 2, the corresponding special
decode enable register should be used instead of a generic one to save
the rather limited generic ones for other decode ranges.
Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/amd/common/block/lpc/espi_util.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3f26a29eb8..4415615545 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,6 +104,9 @@ static int espi_get_unused_io_window(void) */ static int espi_std_io_decode(uint16_t base, size_t size) { + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; + if (size != 1) return -1; |