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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-09 17:43:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-18 20:52:01 +0100
commitc86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a (patch)
tree12171a9fa9d44cc55363defd7a6388ca3a10a898
parentc3e0389c058ea097e80d6d95434b56b6edff8389 (diff)
downloadcoreboot-c86c6b33e8ca32ffa0f0d7e30f35f1fb31fe3b4a.tar.xz
intel cache-as-ram: Move DCACHE_RAM_BASE
Having same memory region set as both WRPROT and WRBACK using MTRRs is undefined behaviour. This could happen if we allow DCACHE_RAM_BASE to be located within CBFS in SPI flash memory and XIP romstage is at the same location. As SPI master by default decodes all of top 16MiB below 4GiB, initial cache-as-ram line fills may have actually read from SPI flash even in the case DCACHE_RAM_BASE was below the nominal 4GiB - ROM_SIZE. There are no reasons to have this as board-specific setting. Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/cpu/intel/ep80579/Kconfig2
-rw-r--r--src/cpu/intel/socket_441/Kconfig2
-rw-r--r--src/cpu/intel/socket_BGA956/Kconfig2
-rw-r--r--src/cpu/intel/socket_FCBGA559/Kconfig2
-rw-r--r--src/cpu/intel/socket_LGA771/Kconfig12
-rw-r--r--src/cpu/intel/socket_mFCPGA478/Kconfig2
-rw-r--r--src/cpu/intel/socket_mPGA478MN/Kconfig2
-rw-r--r--src/cpu/intel/socket_mPGA604/Kconfig2
-rw-r--r--src/mainboard/apple/macbook21/Kconfig8
-rw-r--r--src/mainboard/asus/dsbf/Kconfig8
-rw-r--r--src/mainboard/ibase/mb899/Kconfig8
-rw-r--r--src/mainboard/lenovo/t60/Kconfig8
-rw-r--r--src/mainboard/lenovo/x60/Kconfig8
-rw-r--r--src/mainboard/supermicro/x7db8/Kconfig8
-rw-r--r--src/northbridge/intel/nehalem/Kconfig2
15 files changed, 20 insertions, 56 deletions
diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig
index 062f10167c..dc19ae1c30 100644
--- a/src/cpu/intel/ep80579/Kconfig
+++ b/src/cpu/intel/ep80579/Kconfig
@@ -14,7 +14,7 @@ if CPU_INTEL_EP80579
config DCACHE_RAM_BASE
hex
- default 0xffaf8000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 226919078a..ac249c5755 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
- default 0xffaf8000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 4dd5a60528..6c5e414029 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -8,7 +8,7 @@ if CPU_INTEL_SOCKET_BGA956
config DCACHE_RAM_BASE
hex
- default 0xffaf8000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 9eaa71b58a..d1cc80f7bc 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
config DCACHE_RAM_BASE
hex
- default 0xffafc000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig
index 1df55e61c3..d9bd44ddd8 100644
--- a/src/cpu/intel/socket_LGA771/Kconfig
+++ b/src/cpu/intel/socket_LGA771/Kconfig
@@ -4,3 +4,15 @@ config CPU_INTEL_SOCKET_LGA771
select SSE2
select MMX
select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_SOCKET_LGA771
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xfefc0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif
diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig
index b67f5e622d..075abad961 100644
--- a/src/cpu/intel/socket_mFCPGA478/Kconfig
+++ b/src/cpu/intel/socket_mFCPGA478/Kconfig
@@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
- default 0xffaf8000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mPGA478MN/Kconfig b/src/cpu/intel/socket_mPGA478MN/Kconfig
index 7c4dbc5b29..7d97022cc6 100644
--- a/src/cpu/intel/socket_mPGA478MN/Kconfig
+++ b/src/cpu/intel/socket_mPGA478MN/Kconfig
@@ -9,7 +9,7 @@ if CPU_INTEL_SOCKET_MPGA478MN
config DCACHE_RAM_BASE
hex
- default 0xffaf8000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index d5d668a202..94d6a09b3f 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -22,7 +22,7 @@ config SSE2
config DCACHE_RAM_BASE
hex
- default 0x0ffafc000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index ebf3954dac..4f51a28adf 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -27,14 +27,6 @@ config MAINBOARD_DIR
string
default apple/macbook21
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
if BOARD_APPLE_MACBOOK21
config MAINBOARD_PART_NUMBER
diff --git a/src/mainboard/asus/dsbf/Kconfig b/src/mainboard/asus/dsbf/Kconfig
index 481d4fa1d8..fa0b659e74 100644
--- a/src/mainboard/asus/dsbf/Kconfig
+++ b/src/mainboard/asus/dsbf/Kconfig
@@ -15,14 +15,6 @@ config MAINBOARD_DIR
string
default asus/dsbf
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "DSBF"
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index 4f646acb35..3208a93ee9 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -21,14 +21,6 @@ config MAINBOARD_DIR
string
default ibase/mb899
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "MB899"
diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
index 8e1ee1e70b..9fb46e2eb6 100644
--- a/src/mainboard/lenovo/t60/Kconfig
+++ b/src/mainboard/lenovo/t60/Kconfig
@@ -30,14 +30,6 @@ config MAINBOARD_DIR
string
default lenovo/t60
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T60"
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index eecaf6407e..d80b22d34d 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -33,14 +33,6 @@ config MAINBOARD_DIR
string
default lenovo/x60
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "ThinkPad X60"
diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig
index 82a4ebb27e..fd71254cb1 100644
--- a/src/mainboard/supermicro/x7db8/Kconfig
+++ b/src/mainboard/supermicro/x7db8/Kconfig
@@ -15,14 +15,6 @@ config MAINBOARD_DIR
string
default supermicro/x7db8
-config DCACHE_RAM_BASE
- hex
- default 0xffdf8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
-
config MAINBOARD_PART_NUMBER
string
default "X7DB8 / X7DB8+"
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 281f7279bc..94ca346965 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -39,7 +39,7 @@ config VGA_BIOS_ID
config DCACHE_RAM_BASE
hex
- default 0xff7f0000
+ default 0xfefc0000
config DCACHE_RAM_SIZE
hex