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authorAaron Durbin <adurbin@chromium.org>2015-08-27 14:28:35 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:29:53 +0000
commitce03aaf08c98ce8bc4cb679418f0b82ca50c9a94 (patch)
tree26b9454f0052d8325b02a34dbe3e1db1191206a0
parent394d6993b90d73d4fca7b7500b753e1d18452cd7 (diff)
downloadcoreboot-ce03aaf08c98ce8bc4cb679418f0b82ca50c9a94.tar.xz
skylake: move flash_controller.h to the proper place
I missed this in code review. This should be under the soc directory. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built glados. Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295239 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11542 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/flash_controller.c2
-rw-r--r--src/soc/intel/skylake/include/soc/flash_controller.h (renamed from src/soc/intel/skylake/include/flash_controller.h)6
-rw-r--r--src/soc/intel/skylake/romstage/spi.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c
index f27bcc5484..ab334416c7 100644
--- a/src/soc/intel/skylake/flash_controller.c
+++ b/src/soc/intel/skylake/flash_controller.c
@@ -23,9 +23,9 @@
#include <bootstate.h>
#include <delay.h>
#include <device/pci_ids.h>
-#include <flash_controller.h>
#include <spi_flash.h>
#include <spi-generic.h>
+#include <soc/flash_controller.h>
#include <soc/pci_devs.h>
#include <soc/spi.h>
diff --git a/src/soc/intel/skylake/include/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h
index c79d265248..25cbce9d1f 100644
--- a/src/soc/intel/skylake/include/flash_controller.h
+++ b/src/soc/intel/skylake/include/soc/flash_controller.h
@@ -17,8 +17,8 @@
* Foundation, Inc.,
*/
-#ifndef _FLASH_CONTROLLER__H_
-#define _FLASH_CONTROLLER__H_
+#ifndef _SOC_FLASH_CONTROLLER__H_
+#define _SOC_FLASH_CONTROLLER__H_
#include <rules.h>
#include <arch/io.h>
@@ -173,4 +173,4 @@ enum {
HSFC_FCYCLE_SHIFT = 1,
HSFC_FDBC_SHIFT = 8,
};
-#endif /* _FLASH_CONTROLLER__H_ */
+#endif /* _SOC_FLASH_CONTROLLER__H_ */
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index be6db41d97..2194d21f58 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -18,7 +18,7 @@
* Foundation, Inc.
*/
-#include <flash_controller.h>
+#include <soc/flash_controller.h>
#include <soc/romstage.h>
int early_spi_read(u32 offset, u32 size, u8 *buffer)