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authorPaul Fagerburg <pfagerburg@chromium.org>2019-08-06 14:42:38 -0600
committerMartin Roth <martinroth@google.com>2019-08-11 03:01:30 +0000
commitd366f547445ce0fc14ebf537417f429e329ce191 (patch)
tree1edef5bb6cf1edfe8219c2e542f606e1c2d87f2a
parent0caf834c8f5f3bcbcfe6e9c2e31748769eb13c62 (diff)
downloadcoreboot-d366f547445ce0fc14ebf537417f429e329ce191.tar.xz
kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTF
The Kohaku V24 schematic adds two additional temperature sensors to the EC. Add these to the DPTF tables. Cq-Depend: chromium:1742914 BRANCH=none BUG=b:138578073 TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel. 1. Build EC ``cd ~/trunk/src/platform/ec`` ``make -j BOARD=kohaku`` 2. Program EC ``./util/flash_ec --board=kohaku`` 3. Reboot device 4. Rebuild BIOS ``cd ~/trunk/src/third_party/coreboot`` ``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` 5. Use flashrom to program the BIOS 6. Reboot device 7. Log into the root console (ctrl-alt-F2 or servo) 8. Example thermal sensor information ``grep . /sys/class/thermal/t*/type`` Look for "TSR0" through "TSR3" in the output. Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl28
1 files changed, 22 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl
index 06df7b178f..f6fd907721 100644
--- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl
@@ -17,15 +17,25 @@
#define DPTF_CPU_CRITICAL 105
#define DPTF_TSR0_SENSOR_ID 0
-#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
+#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger"
#define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 1
-#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
+#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V"
#define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 75
+#define DPTF_TSR2_SENSOR_ID 1
+#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA"
+#define DPTF_TSR2_PASSIVE 65
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_TSR3_SENSOR_ID 1
+#define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT"
+#define DPTF_TSR3_PASSIVE 65
+#define DPTF_TSR3_CRITICAL 75
+
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */
@@ -40,11 +50,17 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
- /* CPU Throttle Effect on Ambient (TSR0) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 },
+ /* CPU Throttle Effect on 5V (TSR1) */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+
+ /* Charger Throttle Effect on Charger (TSR0) */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 94, 0, 0, 0, 0 },
+
+ /* CPU Throttle Effect on IA (TSR2) */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
- /* Charger Throttle Effect on Charger (TSR1) */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+ /* CPU Throttle Effect on GT (TSR3) */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 },
})
Name (MPPC, Package ()