Add msi/ms9652_fam10 board.

Updated Timothy's patch to match recent changes in the tree. It's build tested.

Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5180 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

15 files changed, 2390 insertions, 0 deletions

diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig
index 1a85e15afd..7377da7f65 100644
--- a/src/mainboard/msi/Kconfig
+++ b/src/mainboard/msi/Kconfig
@@ -30,6 +30,7 @@ source "src/mainboard/msi/ms7135/Kconfig"
 source "src/mainboard/msi/ms7260/Kconfig"
 source "src/mainboard/msi/ms9185/Kconfig"
 source "src/mainboard/msi/ms9282/Kconfig"
+source "src/mainboard/msi/ms9652_fam10/Kconfig"
 
 endchoice
 
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
new file mode 100644
index 0000000000..ccacb67b15
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -0,0 +1,288 @@
+config BOARD_MSI_MS9652_FAM10
+	bool "MS9652 Fam10 (Speedster K9ND)"
+	select ARCH_X86
+	select CPU_AMD_SOCKET_F_1207
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
+	select SOUTHBRIDGE_NVIDIA_MCP55
+	select SUPERIO_WINBOND_W83627EHG
+	select HAVE_BUS_CONFIG
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select USE_PRINTK_IN_CAR
+	select USE_DCACHE_RAM
+	select HAVE_HARD_RESET
+	select BOARD_ROMSIZE_KB_512
+	select ENABLE_APIC_EXT_ID
+	select AMDMCT
+	select TINY_BOOTBLOCK
+
+config MAINBOARD_DIR
+	string
+	default msi/ms9652_fam10
+	depends on BOARD_MSI_MS9652_FAM10
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xc4000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x0c000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+	hex
+	default 0x04000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONFIG_ACPI_SSDTX_NUM
+	hex
+	default 0x1F
+	depends on BOARD_MSI_MS9652_FAM10
+
+config USE_FALLBACK_IMAGE
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONFIG_USE_FAILOVER_IMAGE
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONFIG_HAVE_FAILOVER_BOOT
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config GENERATE_PIRQ_TABLE
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONFIG_IRQ_SLOT_COUNT
+	hex
+	default 0x0b
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HAVE_OPTION_TABLE
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAX_CPUS
+	int
+	default 8
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+	depends on BOARD_MSI_MS9652_FAM10
+
+config LOGICAL_CPUS
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config IOAPIC
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config SMP
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config STACK_SIZE
+	hex
+	default 0x20000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HEAP_SIZE
+	hex
+	default 0x20000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config USE_OPTION_TABLE
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+	depends on BOARD_MSI_MS9652_FAM10
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_MSI_MS9652_FAM10
+
+config LB_CKS_LOC
+	int
+	default 123
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MS-9256"
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1462
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0x9652
+	depends on BOARD_MSI_MS9652_FAM10
+
+config RAMBASE
+	hex
+	default 0x00200000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config TTYS0_BAUD
+	int
+	default 115200
+	depends on BOARD_MSI_MS9652_FAM10
+
+config TTYS0_BASE
+	hex
+	default 0x3f8
+	depends on BOARD_MSI_MS9652_FAM10
+
+config TTYS0_LCS
+	int
+	default 3
+	depends on BOARD_MSI_MS9652_FAM10
+
+config DEFAULT_CONSOLE_LOGLEVEL
+	int
+	default 9
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAXIMUM_CONSOLE_LOGLEVEL
+	int
+	default 9
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONSOLE_SERIAL8250
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config CONSOLE_VGA
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config PCI_ROM_RUN
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config USBDEBUG_DIRECT
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x20
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x00
+	depends on BOARD_MSI_MS9652_FAM10
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+	depends on BOARD_MSI_MS9652_FAM10
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config VAR_MTRR_HOLE
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config USE_INIT
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config SERIAL_CPU_INIT
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
+
+config APIC_ID_OFFSET
+	hex
+	default 0x00
+	depends on BOARD_MSI_MS9652_FAM10
+
+config LIFT_BSP_APIC_ID
+	bool
+	default 1
+	depends on BOARD_MSI_MS9652_FAM10
+
+config RAMTOP
+	hex
+	default 0x1000000
+	depends on BOARD_MSI_MS9652_FAM10
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+	depends on BOARD_MSI_MS9652_FAM10
+
+config WAIT_BEFORE_CPUS_INIT
+	bool
+	default n
+	depends on BOARD_MSI_MS9652_FAM10
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_01000096.h"
+	depends on BOARD_MSI_MS9652_FAM10
+
+config ID_SECTION_OFFSET
+	hex
+	default 0x80
+	depends on BOARD_MSI_MS9652_FAM10
+
+config HT3_SUPPORT
+	bool
+	default y
+	depends on BOARD_MSI_MS9652_FAM10
diff --git a/src/mainboard/msi/ms9652_fam10/acpi_tables.c b/src/mainboard/msi/ms9652_fam10/acpi_tables.c
new file mode 100644
index 0000000000..0af873c216
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/acpi_tables.c
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
+ * ACPI FADT, FACS, and DSDT table support added by 
+ *
+ * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
+ * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+//#include <../../../northbridge/amd/amdfam10/amdfam10_acpi.h>
+#include <cpu/amd/model_fxx_powernow.h>
+#include <device/pci.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "mb_sysconf.h"
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Not implemented */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned int gsi_base = 0x18;
+	struct mb_sysconf_t *m;
+	//extern unsigned char bus_mcp55[8];
+	//extern unsigned apicid_mcp55;
+	extern void get_bus_conf(void);
+	unsigned sbdn;
+	struct resource *res;
+	device_t dev;
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+	
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB IOAPIC. */
+	dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_1);
+		if (res) {
+			current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				m->apicid_mcp55, res->base,  0);
+		}
+	}
+
+	/* Write NB IOAPIC. */
+	dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_1);
+		if (res) {
+			current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				m->apicid_mcp55++, res->base,  gsi_base);
+		}
+	}
+
+	/* IRQ9 ACPI active low. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* IRQ0 -> APIC IRQ2. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 0, 2, 0x0);	
+
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapic_nmis(current,
+		MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	//k8acpi_write_vars();
+	//amd_model_fxx_generate_powernow(0, 0, 0);
+	//return (unsigned long) (acpigen_get_current());
+	return 0;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_mcfg_t *mcfg;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_slit_t *slit;
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT table. */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* We explicitly add these tables later on: */
+	printk_debug("ACPI:     * FACS\n");
+
+	/* we should align FACS to 64B as per ACPI specs */
+	current = ALIGN(current, 64);
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode)->length;
+	memcpy((void *) dsdt, (void *) AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
+	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+	printk_debug("ACPI:     * DSDT @ %08x Length %x\n", dsdt,
+		     dsdt->length);
+	printk_debug("ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk_debug("ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET timers Linux wants an MADT. */
+	printk_debug("ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	printk_debug("ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+
+	printk_debug("ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	printk_debug("ACPI:    * SLIT\n");
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current+=slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	printk_debug("ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/msi/ms9652_fam10/chip.h b/src/mainboard/msi/ms9652_fam10/chip.h
new file mode 100644
index 0000000000..556dc7ea1d
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/chip.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+//	int fixup_scsi;
+//	int fixup_vga;
+};
diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout
new file mode 100644
index 0000000000..07492b6695
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/cmos.layout
@@ -0,0 +1,119 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        quad_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        reserved_memory
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     200Mhz
+8     1     166Mhz
+8     2     133Mhz
+8     3     100Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb
new file mode 100644
index 0000000000..ecc71b6af9
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb
@@ -0,0 +1,155 @@
+## Copyright (C) 2010 Raptor Engineering
+## Written by Timothy Pearson <tpearson@raptorengineeringinc.com> for Raptor Engineering.
+##
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+
+chip northbridge/amd/amdfam10/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F_1207
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdfam10 #mc0
+			device pci 18.0 on	# SB on HT link 0.0
+				chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627ehg
+							device pnp 2e.0 on #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  SERIAL_FLASH
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  WDTO_PLED
+							device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+							device pnp 2e.106 off		# Serial flash
+								io 0x60 = 0x100
+							end
+							device pnp 2e.207 on		# MIDI
+								io 0x62 = 0x330
+								irq 0x70 = 0xa
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#						chip drivers/generic/generic #PCIXA Slot1
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot2
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #PCI Slot1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #Master MCP55 PCI-E
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #Slave MCP55 PCI-E
+#							device i2c 55 on end
+#						end
+#						chip drivers/generic/generic #MAC EEPROM
+#							device i2c 51 on end
+#						end
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.1 on end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end	# HT 1.0
+			device pci 18.0 on end	# HT 2.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end # mc0
+
+	end # PCI domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	end
+end #root_complex
diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl
new file mode 100644
index 0000000000..678d339ce3
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl
@@ -0,0 +1,302 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
+ * (C) Copyright 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
+ * (C) Copyright 2009 Harald Gutmann <harald.gutmann@gmx.net>
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 */
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (\_SB)
+	{
+		/* Top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			External (BUSN)
+			External (MMIO)
+			External (PCIO)
+			External (SBLK)
+			External (TOM1)
+			External (HCLK)
+			External (SBDN)
+			External (HCDN)
+                    
+			Method (_CRS, 0, NotSerialized)
+                        {
+				Name (BUF0, ResourceTemplate ()
+				{
+					IO (Decode16,
+					0x0CF8,             // Address Range Minimum
+					0x0CF8,             // Address Range Maximum
+					0x01,               // Address Alignment
+					0x08,               // Address Length
+					)
+					WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,             // Address Space Granularity
+					0x0000,             // Address Range Minimum
+					0x0CF7,             // Address Range Maximum
+					0x0000,             // Address Translation Offset
+					0x0CF8,             // Address Length
+					,, , TypeStatic)
+				})
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				 */
+				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
+				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
+				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
+				Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
+				Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
+				Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
+				Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
+				Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
+				Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
+			})
+
+			Device (PEBF) /* PCI-E Bridge F */
+			{
+				Name (_ADR, 0x000F0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x07)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+				})
+			}
+
+			Device (PEBE) /* PCI-E Bridge E */
+			{
+				Name (_ADR, 0x000E0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x06)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+
+			Device (PEBD) /* PCI-E Bridge D */
+			{
+				Name (_ADR, 0x000D0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x05)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },
+				})
+			}
+
+			Device (PEBC) /* PCI-E Bridge C */
+			{
+				Name (_ADR, 0x000C0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x04)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+				})
+			}
+
+			Device (PEBB) /* PCI-E Bridge B */
+			{
+				Name (_ADR, 0x000B0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x03)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+				})
+			}
+
+			Device (PEBA) /* PCI-E Bridge A */
+			{
+				Name (_ADR, 0x000A0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x02)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+
+			Device (PCID)	/* PCI Device */
+			{
+				Name (_ADR, 0x00060000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x01)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
+					Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */
+					Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
+					Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
+					Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */
+					Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
+					Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
+					Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
+					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
+					Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
+					Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+		}
+
+		Device (ISA) {
+			Name (_ADR, 0x000010000)
+
+			/* PS/2 keyboard (seems to be important for WinXP install) */
+			Device (KBD)
+			{
+				Name (_HID, EisaId ("PNP0303"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (TMP0, ResourceTemplate () {
+						IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+						IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+						IRQNoFlags () {1}
+					})
+					Return (TMP0)
+				}
+			}
+
+			/* PS/2 mouse */
+			Device (MOU)
+			{
+				Name (_HID, EisaId ("PNP0F13"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (TMP1, ResourceTemplate () {
+						IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+						IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+						IRQNoFlags () {12}
+					})
+					Return (TMP1)
+				}
+			}
+
+			/* PS/2 floppy controller */
+			Device (FDC0)
+			{
+				Name (_HID, EisaId ("PNP0700"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (BUF0, ResourceTemplate () {
+						IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+						IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+						IRQNoFlags () {6}
+						DMA (Compatibility, NotBusMaster, Transfer8) {2}
+					})
+					Return (BUF0)
+				}
+			}
+			/* Parallel Port */
+			Device (LPT1)
+			{
+				Name (_HID, EisaId ("PNP0400"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (BUF1, ResourceTemplate () {
+						IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) 
+						IRQNoFlags () {7}
+					})
+					Return (BUF1)
+				}
+			}
+			/* Parallel Port ECP */
+			Device (ECP1)
+			{
+				Name (_HID, EisaId ("PNP0401"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (BUF1, ResourceTemplate () {
+						IO (Decode16, 0x0378, 0x0378, 0x01, 0x04) 
+						IO (Decode16, 0x0778, 0x0778, 0x01, 0x04)
+						IRQNoFlags() {7}
+						DMA (Compatibility, NotBusMaster, Transfer8) {0,1,3}
+					})
+					Return (BUF1)
+				}
+			}
+		}
+	}
+}
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
new file mode 100644
index 0000000000..35ad714b13
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/quadcore.h>
+#endif
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include <stdlib.h>
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+/* Here you only need to set value in pci1234 for HT-IO that could be
+installed or not You may need to preset pci1234 for HTIO board, please
+refer to src/northbridge/amd/amdfam10/get_pci1234.c for detail */
+static u32 pci1234x[] = {
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc, 0x0000ffc,
+	0x0000ffc, 0x0000ffc,
+	};
+
+
+/* HT Chain device num, actually it is unit id base of every ht device
+in chain, assume every chain only have 4 ht device at most */
+
+static unsigned hcdnx[] = {
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020, 0x20202020, 0x20202020, 0x20202020,
+	0x20202020, 0x20202020,
+};
+
+extern void get_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	unsigned apicid_base;
+	struct mb_sysconf_t *m;
+
+	device_t dev;
+	int i, j;
+
+	printk_spew("get_bus_conf()\n");
+
+	if(get_bus_conf_done==1) return; //do it only once
+
+	get_bus_conf_done = 1;
+
+	sysconf.mb = &mb_sysconf;
+
+	m = sysconf.mb;
+	memset(m, 0, sizeof(struct mb_sysconf_t));
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for(i=0;i<sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	m->bus_type[0] = 1; //pci
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
+
+		/* MCP55 */
+		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+		if (dev) {
+			m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		}
+		else {
+			printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
+		}
+
+		for(i=2; i<8;i++) {
+			dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
+			if (dev) {
+				m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			}
+			else {
+				printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
+			}
+		}
+
+	for(i=0; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+		unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
+		unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
+		for (j = busn; j <= busn_max; j++)
+			m->bus_type[j] = 1;
+		if(m->bus_isa <= busn_max)
+			m->bus_isa = busn_max + 1;
+		printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
+	}
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+	printk_spew("CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n");
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+	printk_spew("CONFIG_LOGICAL_CPUS==0: apicid_base: %08x\n");
+#endif
+	m->apicid_mcp55 = apicid_base+0;
+}
diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c
new file mode 100644
index 0000000000..ea870a147b
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file was generated by getpir.c, do not modify! 
+ * (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdfam10_sysconf.h>
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+		uint8_t slot, uint8_t rfu)
+{
+	pirq_info->bus = bus; 
+	pirq_info->devfn = devfn;
+		pirq_info->irq[0].link = link0;
+		pirq_info->irq[0].bitmap = bitmap0;
+		pirq_info->irq[1].link = link1;
+		pirq_info->irq[1].bitmap = bitmap1;
+		pirq_info->irq[2].link = link2;
+		pirq_info->irq[2].bitmap = bitmap2;
+		pirq_info->irq[3].link = link3;
+		pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+extern void get_bus_conf(void);
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	unsigned slot_num;
+	uint8_t *v;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+	uint8_t sum=0;
+	int i;
+
+	get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+	pirq = (void *)(addr);
+	v = (uint8_t *)(addr);
+	
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version  = PIRQ_VERSION;
+	
+	pirq->rtr_bus = m->bus_mcp55[0];
+	pirq->rtr_devfn = ((sbdn+6)<<3)|0;
+
+	pirq->exclusive_irqs = 0;
+	
+	pirq->rtr_vendor = 0x10de;
+	pirq->rtr_device = 0x0370;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *) ( &pirq->checksum + 1);
+	slot_num = 0;
+//pci bridge
+	write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+	
+	for(i=1; i< sysconf.hc_possible_num; i++) {
+		if(!(sysconf.pci1234[i] & 0x1) ) continue;
+		unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
+		unsigned devn = sysconf.hcdn[i] & 0xff;
+
+		write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+		pirq_info++; slot_num++;
+	}
+
+#if CONFIG_CBB
+	write_pirq_info(pirq_info, CONFIG_CBB, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++; slot_num++;
+	if(sysconf.nodes>32) {
+		write_pirq_info(pirq_info, CONFIG_CBB-1, (0<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+		pirq_info++; slot_num++;
+	}
+#endif
+
+	pirq->size = 32 + 16 * slot_num; 
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];	
+
+	sum = pirq->checksum - sum;
+
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk_info("done.\n");
+
+	return	(unsigned long) pirq_info;
+
+}
diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
new file mode 100644
index 0000000000..d1faac990d
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("MSI MS-9652 Mainboard (Family 10)")
+};
diff --git a/src/mainboard/msi/ms9652_fam10/mb_sysconf.h b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
new file mode 100644
index 0000000000..83f9dbab28
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	unsigned char bus_isa;
+	unsigned char bus_mcp55[8]; //1
+	unsigned apicid_mcp55;
+	unsigned bus_type[256]; 
+
+};
+
+#endif
+
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
new file mode 100644
index 0000000000..3ddae1ccdc
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+extern void get_bus_conf(void);
+
+void *smp_write_config_table(void *v)
+{
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "MSI     ";
+	static const char productid[12] = "K9ND MS-9652";
+	struct mp_config_table *mc;
+	struct mb_sysconf_t *m;
+	unsigned sbdn;
+
+	int i,j;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
+
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc); /* initially just the header */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0; /* not yet computed */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0; /* No entries yet... */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+	m = sysconf.mb;
+
+/*Bus:		Bus ID	Type*/
+	/* define bus and isa numbers */
+	for(j= 0; j < 256 ; j++) {
+		if(m->bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+	}
+	smp_write_bus(mc, m->bus_isa, "ISA   ");
+
+/*I/O APICs:	APIC ID	Version	State		Address*/
+	{
+		device_t dev;
+		struct resource *res;
+		uint32_t dword;
+
+		dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+		if (dev) {
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			if (res) {
+				smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
+			}
+
+			dword = 0x43c6c643;
+			pci_write_config32(dev, 0x7c, dword);
+
+			dword = 0x81001a00;
+			pci_write_config32(dev, 0x80, dword);
+
+			dword = 0xd00012d2;
+			pci_write_config32(dev, 0x84, dword);
+
+		}
+
+
+	}
+
+			/*I/O Ints:	Type	Polarity    Trigger			Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
+
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
+
+	for(j=7; j>=2; j--) {
+		if(!m->bus_mcp55[j]) continue;
+		for(i=0;i<4;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+		}
+	}
+
+	for(j=0; j<1; j++)
+		for(i=0;i<4;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
+		}
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c
new file mode 100644
index 0000000000..4fe4f4d711
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c
@@ -0,0 +1,287 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00004000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n 
+		 * [31:25] Reserved
+		 */
+		/* Verified against board configuration registers after normal proprietary BIOS boot */
+		//PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001033,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration region i
+		 */
+		/* Verified against board configuration registers after normal proprietary BIOS boot */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
+
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
new file mode 100644
index 0000000000..96806609d9
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -0,0 +1,389 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __PRE_RAM__
+
+#define RAMINIT_SYSINFO 1
+
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 1
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#define FAM10_SET_FIDVID 1
+#define FAM10_SET_FIDVID_CORE_RANGE 0
+
+#define DBGP_DEFAULT 7
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+ static void post_code(u8 value) {
+ 	outb(value, 0x80);
+ }
+
+#if CONFIG_USE_FAILOVER_IMAGE==0
+#include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "lib/ramtest.c"
+
+#include <cpu/amd/model_10xxx_rev.h>
+
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
+
+#if CONFIG_USE_FAILOVER_IMAGE==0
+
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdfam10/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+static void memreset_setup(void)
+{
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+	/* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "northbridge/amd/amdht/ht_wrapper.c"
+
+#include "include/cpu/x86/mem.h"
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/raminit_amdmct.c"
+#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+
+#include "resourcemap.c"
+
+#include "cpu/amd/quadcore/quadcore.c"
+
+#define MCP55_NUM 1
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 1
+
+#define MCP55_MB_SETUP \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
+
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
+
+#include "cpu/amd/car/copy_and_run.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_10xxx/init_cpus.c"
+
+#include "cpu/amd/model_10xxx/fidvid.c"
+
+#endif
+
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+
+static void sio_setup(void)
+{
+
+        unsigned value;
+        uint32_t dword;
+        uint8_t byte;
+
+        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20;
+        pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
+
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
+        dword |= (1<<0);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
+
+
+}
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	unsigned last_boot_normal_x = last_boot_normal();
+
+	/* Is this a cpu only reset? or Is this a secondary cpu? */
+	if ((cpu_init_detectedx) || (!boot_cpu())) {
+		if (last_boot_normal_x) {
+			goto normal_image;
+		} else {
+			goto fallback_image;
+		}
+	}
+
+	/* Nothing special needs to be done to find bus 0 */
+	/* Allow the HT devices to be found */
+
+	set_bsp_node_CHtExtNodeCfgEn();
+	enumerate_ht_chain();
+
+	sio_setup();
+
+	/* Setup the mcp55 */
+	mcp55_enable_rom();
+
+	/* Is this a deliberate reset by the bios */
+	if (bios_reset_detected() && last_boot_normal_x) {
+		goto normal_image;
+	}
+	/* This is the primary cpu how should I boot? */
+	else if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	__asm__ volatile ("jmp __normal_image"
+		: /* outputs */
+		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+		);
+
+ fallback_image:
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+	__asm__ volatile ("jmp __fallback_image"
+		: /* outputs */
+		: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+		)
+#endif
+	;
+}
+#endif
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+    #if CONFIG_USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if CONFIG_USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);
+    #endif
+	real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if CONFIG_USE_FAILOVER_IMAGE==0
+#include "spd_addr.h"
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+	u32 bsp_apicid = 0;
+	u32 val;
+	u8 reg;
+	u32 wants_reset;
+	msr_t msr;
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+	}
+
+	post_code(0x32);
+
+	pnp_enter_ext_func_mode(SERIAL_DEV);
+	/* We have 24MHz input. */
+	reg = pnp_read_config(SERIAL_DEV, 0x24);
+	pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
+	pnp_exit_ext_func_mode(SERIAL_DEV);
+
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+	printk_debug("\n");
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+#endif
+
+	val = cpuid_eax(1);
+	printk_debug("BSP Family_Model: %08x \n", val);
+	printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+	printk_debug("bsp_apicid = %02x \n", bsp_apicid);
+	printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+	update_microcode(val);
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+	printk_debug("finalize_node_setup done \n");
+
+	/* Setup any mainboard PCI settings etc. */
+	printk_debug("setup_mb_resource_map begin \n");
+	setup_mb_resource_map();
+	printk_debug("setup_mb_resource_map end \n");
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	 * It would be nice to fixup prink spinlocks for ROM XIP mode.
+	 * I think it could be done by putting the spinlock flag in the cache
+	 * of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk_debug("start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	printk_debug("wait_all_other_cores_started()\n");
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+#if FAM10_SET_FIDVID == 1
+	msr = rdmsr(0xc0010071);
+	printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+
+	/* FIXME: The sb fid change may survive the warm reset and only
+	 * need to be done once.*/
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	wants_reset = mcp55_early_setup_x();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	if (wants_reset)
+		printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk_debug("fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+	post_code(0x3D);
+
+	printk_debug("enable_smbus()\n");
+	enable_smbus();
+	post_code(0x3E);
+
+	memreset_setup();
+	post_code(0x40);
+
+	printk_debug("raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+	printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+
+#endif
diff --git a/src/mainboard/msi/ms9652_fam10/spd_addr.h b/src/mainboard/msi/ms9652_fam10/spd_addr.h
new file mode 100644
index 0000000000..915ee8bd7c
--- /dev/null
+++ b/src/mainboard/msi/ms9652_fam10/spd_addr.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * This file defines the SPD addresses for the mainboard. Must be included in
+ * cache_as_ram_auto.c
+ */
+
+#define RC00 0
+#define RC01 1
+#define RC02 2
+#define RC03 3
+#define RC04 4
+#define RC05 5
+#define RC06 6
+#define RC07 7
+#define RC08 8
+#define RC09 9
+#define RC10 10
+#define RC11 11
+#define RC12 12
+#define RC13 13
+#define RC14 14
+#define RC15 15
+#define RC16 16
+#define RC17 17
+#define RC18 18
+#define RC19 19
+#define RC20 20
+#define RC21 21
+#define RC22 22
+#define RC23 23
+#define RC24 24
+#define RC25 25
+#define RC26 26
+#define RC27 27
+#define RC28 28
+#define RC29 29
+#define RC30 30
+#define RC31 31
+
+#define RC32 32
+#define RC33 33
+#define RC34 34
+#define RC35 35
+#define RC36 36
+#define RC37 37
+#define RC38 38
+#define RC39 39
+#define RC40 40
+#define RC41 41
+#define RC42 42
+#define RC43 43
+#define RC44 44
+#define RC45 45
+#define RC46 46
+#define RC47 47
+#define RC48 48
+#define RC49 49
+#define RC50 50
+#define RC51 51
+#define RC52 52
+#define RC53 53
+#define RC54 54
+#define RC55 55
+#define RC56 56
+#define RC57 57
+#define RC58 58
+#define RC59 59
+#define RC60 60
+#define RC61 61
+#define RC62 62
+#define RC63 63
+
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+#define DIMM4 0x54
+#define DIMM5 0x55
+#define DIMM6 0x56
+#define DIMM7 0x57
+
+
+static const u8 spd_addr[] = {
+	//first node
+	RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+	//second node
+	RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
+#endif
+};
+