The DBM90T code sets bit 10 in _PSS as part of the control value, but

bit 10 is part of NewVID. That means the resulting VID is wrong and
causes the processor to crash.
The Pistachio code has the same bug.

This patch fixes the wrong setting and changes control from a magic and
incorrect unexplained value (0xE8202C00) to a combination of explained
values and shifts which has the right value (0xE8202800).

It is tested on my machine and it survived 200 changes from minimum to
maximum frequency every 100 ms under heavy load and under no load.

In the long term we want to consolidate all AMD FIDVID code into one
generic library file.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Maggie Li has tested it on her DBM690T board. It is ok.
Acked-by: Maggie li <Maggie.li@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 29 insertions, 11 deletions

diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c
index 987eeae8b8..dc382d6cef 100644
--- a/src/mainboard/amd/dbm690t/acpi_tables.c
+++ b/src/mainboard/amd/dbm690t/acpi_tables.c
@@ -260,7 +260,7 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 
 	/* Get the multipier of the fid frequency */
 	/*
-	 * Fid multiplier is always 100 revF and revG.

+	 * Fid multiplier is always 100 revF and revG.
 	 */
 	fid_multiplier = 100;
 
@@ -400,10 +400,10 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 		Pstate_num++;
 	}
 
-	/* Print Pstate feq,vid,volt,power */
+	/* Print Pstate freq,vid,volt,power */
 
 	for (index = 0; index < Pstate_num; index++) {
-		printk_info("Pstate_feq[%d] = %dMHz\t", index,
+		printk_info("Pstate_freq[%d] = %dMHz\t", index,
 			    Pstate_feq[index]);
 		printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
 		printk_info("Pstate_volt[%d] = %dmv\t", index,
@@ -414,8 +414,11 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 
 	/*
 	 * Modify the DSDT Table to put the actural _PSS package
-	 * corefeq-->Pstate_feq[index] power-->Pstate_power[index] transitionlatency-->0x64 busmasterlatency-->0x7,
-	 * control-->0xE8202C00| Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * corefeq-->Pstate_feq[index]
+	 * power-->Pstate_power[index]
+	 * transitionlatency-->0x64
+	 * busmasterlatency-->0x7,
+	 * control--> 0xE8202800| Pstate_vid[index]<<6 | Pstate_fid[index]
 	 * status --> Pstate_vid[index]<<6 | Pstate_fid[index]
 	 * Get the _PSS control method Sig.
 	 */
@@ -461,7 +464,13 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 				transitionlatency = 0x64;
 				busmasterlatency = 0x7;
 				control =
-				    0xE8202C00 | (Pstate_vid[index] << 6) |
+				    (0x3 << 30) | /* IRT */
+				    (0x2 << 28) | /* RVO */
+				    (0x1 << 27) | /* ExtType */
+				    (0x2 << 20) | /* PLL_LOCK_TIME */
+				    (0x0 << 18) | /* MVS */
+				    (0x5 << 11) | /* VST */
+				    (Pstate_vid[index] << 6) |
 				    Pstate_fid[index];
 				status =
 				    (Pstate_vid[index] << 6) |
diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c
index dfb9167481..dc382d6cef 100644
--- a/src/mainboard/amd/pistachio/acpi_tables.c
+++ b/src/mainboard/amd/pistachio/acpi_tables.c
@@ -400,10 +400,10 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 		Pstate_num++;
 	}
 
-	/* Print Pstate feq,vid,volt,power */
+	/* Print Pstate freq,vid,volt,power */
 
 	for (index = 0; index < Pstate_num; index++) {
-		printk_info("Pstate_feq[%d] = %dMHz\t", index,
+		printk_info("Pstate_freq[%d] = %dMHz\t", index,
 			    Pstate_feq[index]);
 		printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
 		printk_info("Pstate_volt[%d] = %dmv\t", index,
@@ -414,8 +414,11 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 
 	/*
 	 * Modify the DSDT Table to put the actural _PSS package
-	 * corefeq-->Pstate_feq[index] power-->Pstate_power[index] transitionlatency-->0x64 busmasterlatency-->0x7,
-	 * control-->0xE8202C00| Pstate_vid[index]<<6 | Pstate_fid[index]
+	 * corefeq-->Pstate_feq[index]
+	 * power-->Pstate_power[index]
+	 * transitionlatency-->0x64
+	 * busmasterlatency-->0x7,
+	 * control--> 0xE8202800| Pstate_vid[index]<<6 | Pstate_fid[index]
 	 * status --> Pstate_vid[index]<<6 | Pstate_fid[index]
 	 * Get the _PSS control method Sig.
 	 */
@@ -461,7 +464,13 @@ u32 pstates_algorithm(acpi_header_t * dsdt)
 				transitionlatency = 0x64;
 				busmasterlatency = 0x7;
 				control =
-				    0xE8202C00 | (Pstate_vid[index] << 6) |
+				    (0x3 << 30) | /* IRT */
+				    (0x2 << 28) | /* RVO */
+				    (0x1 << 27) | /* ExtType */
+				    (0x2 << 20) | /* PLL_LOCK_TIME */
+				    (0x0 << 18) | /* MVS */
+				    (0x5 << 11) | /* VST */
+				    (Pstate_vid[index] << 6) |
 				    Pstate_fid[index];
 				status =
 				    (Pstate_vid[index] << 6) |