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authorCeri Coburn <ceri.coburn@gmail.com>2007-05-10 22:46:17 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-05-10 22:46:17 +0000
commite1dd5e96c83dee11d0dbd6c5b7ab2a3651d9f7ec (patch)
treeb0d90fb972613f292fddc987ac5a8048ca29f732
parent00dc8595a63483e0cc93e8518993d12f4fe8227a (diff)
downloadcoreboot-e1dd5e96c83dee11d0dbd6c5b7ab2a3651d9f7ec.tar.xz
Fixed a bug within the 440BX RAM size calculation. Since the DRB values
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB. Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com> Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/intel/i440bx/northbridge.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 3dbfe1bad7..3870de866f 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -112,7 +112,8 @@ static void pci_domain_set_resources(device_t dev)
* the physical memory. The units are ticks of 8MB
* i.e. 1 means 8MB.
*/
- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)) << 15;
+ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)) << 13;
+ printk_debug("Setting RAM size to %d MB\n", tomk >> 10);
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {