summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorVenkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>2020-04-07 16:33:33 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-04-29 03:01:37 +0000
commiteb148d88d1af5b4fb409794e974f89cf2705741a (patch)
treeacc30caf9e0a2873edf8a06ef991249a4b41432b
parentcd41fa378d03eb2509d5757c441f242bc3f98a6f (diff)
downloadcoreboot-eb148d88d1af5b4fb409794e974f89cf2705741a.tar.xz
mb/google/volteer: Work around TPM issue by enabling GPIO PM in S0ix
Setting the default values for GPIO community power management, causes issues in detecting TPM interrupts. So to avoid that GPIO PM has to be disabled in devicetree. But for S0ix it is needed. This patch implements a workaround in ASL code to enable GPIO PM on S0ix entry and disable it on S0ix exit. This patch adds the following three platform specific methods. 1. MS0X to enable power management features for GPIO communities on entry and on exit, it disables them. 2. MPTS to enable power management features for GPIO communities when preparing to sleep. 3. MWAK to disable power management features for GPIO communities on waking up. BUG=b:148892882 BRANCH=none TEST="Boot with this change on volteer proto1 and check for GPIO community config with debugger" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: If522c82c0069a4bf5738beb73a2b4f11ed6f51d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40261 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/volteer/dsdt.asl6
-rw-r--r--src/mainboard/google/volteer/mainboard.asl48
2 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index af881ae859..450835db03 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -32,11 +32,17 @@ DefinitionBlock(
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
}
+ /* Mainboard hooks */
+ #include "mainboard.asl"
}
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+ /* Include Low power idle table for a short term workaround to enable
+ S0ix. Once cr50 pulse width is fixed, this can be removed. */
+ #include <soc/intel/common/acpi/lpit.asl>
+
// Chrome OS Embedded Controller
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl
new file mode 100644
index 0000000000..d58822d719
--- /dev/null
+++ b/src/mainboard/google/volteer/mainboard.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+ For (Local0 = 0, Local0 < 6, Local0++)
+ {
+ \_SB.PCI0.CGPM (Local0, Arg0)
+ }
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+ PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+ PGPM (0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.LPID._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+ If (Arg0 == 1) {
+ /* S0ix Entry */
+ PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ } Else {
+ /* S0ix Exit */
+ PGPM (0)
+ }
+}