arch/riscv: Don't hardcode CSR numbers anymore

They are hopefully stable enough by now.

TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS,
     with and without this patch, results in the same coreboot.rom.

Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>

1 files changed, 2 insertions, 7 deletions

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index d9bae2aac3..0061847c01 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -59,11 +59,6 @@ void mstatus_init(void)
 		set_csr(medeleg, delegate);
 	}
 
-	// Enable all user/supervisor-mode counters using
-	// v1.10 register addresses.
-	// They moved from the earlier spec.
-	// Until we trust our toolchain use the hardcoded constants.
-	// These were in flux and people who get the older toolchain
-	// will have difficult-to-debug failures.
-	write_csr(/*mcounteren*/0x306, 7);
+	// Enable all user/supervisor-mode counters
+	write_csr(mcounteren, 7);
 }