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authorUwe Hermann <uwe@hermann-uwe.de>2008-10-21 16:27:38 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2008-10-21 16:27:38 +0000
commit039255c59c11863e00a64c47c487fe59c5c12097 (patch)
tree90c2e40abef898a3bf50852a031e0734bf00e9cb
parent657a6dc390871721711c2becc8501d05095891e5 (diff)
downloadcoreboot-039255c59c11863e00a64c47c487fe59c5c12097.tar.xz
I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
Also, use more readable #defines instead of hardcoded config ports for PM/PM2 related functions, and simplify them a bit. Build-tested with the AMD dbm690t target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/southbridge/amd/sb600/sb600.c16
-rw-r--r--src/southbridge/amd/sb600/sb600.h6
-rw-r--r--src/southbridge/amd/sb600/sb600_early_setup.c12
3 files changed, 17 insertions, 17 deletions
diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c
index b1b17f0022..ef941ddb01 100644
--- a/src/southbridge/amd/sb600/sb600.c
+++ b/src/southbridge/amd/sb600/sb600.c
@@ -60,13 +60,13 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
}
}
-static void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
}
-static u8 pmio_read_index(unsigned long port_base, u8 reg)
+static u8 pmio_read_index(u16 port_base, u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
@@ -74,26 +74,22 @@ static u8 pmio_read_index(unsigned long port_base, u8 reg)
void pm_iowrite(u8 reg, u8 value)
{
- unsigned long port_base = 0xcd6;
- pmio_write_index(port_base, reg, value);
+ pmio_write_index(PM_INDEX, reg, value);
}
u8 pm_ioread(u8 reg)
{
- unsigned long port_base = 0xcd6;
- return pmio_read_index(port_base, reg);
+ return pmio_read_index(PM_INDEX, reg);
}
void pm2_iowrite(u8 reg, u8 value)
{
- unsigned long port_base = 0xcd0;
- pmio_write_index(port_base, reg, value);
+ pmio_write_index(PM2_INDEX, reg, value);
}
u8 pm2_ioread(u8 reg)
{
- unsigned long port_base = 0xcd0;
- return pmio_read_index(port_base, reg);
+ return pmio_read_index(PM2_INDEX, reg);
}
static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 24b028de3d..ce8bce446a 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -23,6 +23,12 @@
#include <device/pci_ids.h>
#include "chip.h"
+/* Power management index/data registers */
+#define PM_INDEX 0xcd6
+#define PM_DATA 0xcd7
+#define PM2_INDEX 0xcd0
+#define PM2_DATA 0xcd1
+
extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value);
diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c
index 50acc0e59b..7f588e9ce7 100644
--- a/src/southbridge/amd/sb600/sb600_early_setup.c
+++ b/src/southbridge/amd/sb600/sb600_early_setup.c
@@ -18,24 +18,22 @@
*/
#include <arch/cpu.h>
+#include "sb600.h"
#include "sb600_smbus.c"
#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
/*SIZE 0x40 */
-
-/* Copied from sb600.c
-* 0xCD6-0xCD7 is power management I/O register.*/
static void pmio_write(u8 reg, u8 value)
{
- outb(reg, 0xCD6);
- outb(value, 0xCD6 + 1);
+ outb(reg, PM_INDEX);
+ outb(value, PM_INDEX + 1);
}
static u8 pmio_read(u8 reg)
{
- outb(reg, 0xCD6);
- return inb(0xCD6 + 1);
+ outb(reg, PM_INDEX);
+ return inb(PM_INDEX + 1);
}
/* Get SB ASIC Revision.*/