summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMartin Roth <martin.roth@se-eng.com>2014-11-16 17:32:56 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-05 16:19:45 +0100
commit09dd70ebb8f31b36d536f05af289e8edc069c893 (patch)
tree647abf9a48259029b3e718487299e7e2c171d8e8
parent3cf6aea871e4b5929959124356a7775ff21d65ac (diff)
downloadcoreboot-09dd70ebb8f31b36d536f05af289e8edc069c893.tar.xz
drivers/intel/fsp: add upd macros and #defines
Add macros and #defines for working with the UPD data. This makes the code look much cleaner. Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include the fsp_values header instead. This fixes a conflict. Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7487 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r--src/drivers/intel/fsp/fsp_util.h24
-rw-r--r--src/drivers/intel/fsp/fsp_values.h41
-rw-r--r--src/northbridge/intel/fsp_rangeley/chip.h3
3 files changed, 66 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h
index db8b6dec1d..64a5e7f333 100644
--- a/src/drivers/intel/fsp/fsp_util.h
+++ b/src/drivers/intel/fsp/fsp_util.h
@@ -21,6 +21,7 @@
#define FSP_UTIL_H
#include <chipset_fsp_util.h>
+#include "fsp_values.h"
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
@@ -92,4 +93,27 @@ void update_mrc_cache(void *unused);
extern void *FspHobListPtr;
#endif
+#define UPD_DEFAULT_CHECK(member) \
+ if (config->member != UPD_DEFAULT) { \
+ UpdData->member = config->member - 1; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_SPD_CHECK(member) \
+ if (config->member == UPD_SPD_ADDR_DISABLED) { \
+ UpdData->member = 0x00; \
+ } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \
+ UpdData->member = config->member; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_DEVICE_CHECK(devicename, member, statement) \
+ case devicename: \
+ UpdData->member = dev->enabled; \
+ printk(FSP_INFO_LEVEL, statement "%s\n", \
+ UpdData->member?"Enabled":"Disabled"); \
+ break;
+
#endif /* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp/fsp_values.h b/src/drivers/intel/fsp/fsp_values.h
new file mode 100644
index 0000000000..e5098bb9ee
--- /dev/null
+++ b/src/drivers/intel/fsp/fsp_values.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef FSP_VALUES_H
+#define FSP_VALUES_H
+
+#ifndef FSP_DEBUG_LEVEL
+# define FSP_DEBUG_LEVEL BIOS_SPEW
+#endif
+
+#ifndef FSP_INFO_LEVEL
+# define FSP_INFO_LEVEL BIOS_DEBUG
+#endif
+
+#define INCREMENT_FOR_DEFAULT(x) (x+1)
+
+#define UPD_DEFAULT 0x00
+#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0)
+#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1)
+#define UPD_USE_DEVICETREE 0xff
+
+#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT
+#define UPD_SPD_ADDR_DISABLED 0xFF
+
+#endif
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
index 24609a107e..80a22bf1ea 100644
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -21,6 +21,7 @@
#define _FSP_RANGELEY_CHIP_H_
#include <arch/acpi.h>
+#include <drivers/intel/fsp/fsp_values.h>
struct northbridge_intel_fsp_rangeley_config {
@@ -36,8 +37,6 @@ struct northbridge_intel_fsp_rangeley_config {
uint8_t SpdBaseAddress_1_0;
uint8_t SpdBaseAddress_1_1;
-#define UPD_ENABLE 1
-#define UPD_DISABLE 0
uint8_t EnableLan;
uint8_t EnableSata2;
uint8_t EnableSata3;