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| author | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:36:46 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:36:46 +0000 |
| commit | 0da5cdeac2b787f5665c3cbc208c3c2adcf331c1 (patch) | |
| tree | d8bfaaf4daebbfabcf2bc980f5639a852e28a4c9 | |
| parent | 8ae8c8822068ef1722c08073ffa4ecc25633cbee (diff) | |
| download | coreboot-0da5cdeac2b787f5665c3cbc208c3c2adcf331c1.tar.xz | |
Additional early AMD8111 southbridge support for Barcelona platforms.
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_early_ctrl.c | 36 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_early_smbus.c | 12 |
2 files changed, 32 insertions, 16 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c index 9d40076bea..0e34c31c1e 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c +++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c @@ -14,25 +14,33 @@ static unsigned get_sbdn(unsigned bus) } -static void hard_reset(void) +static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; - unsigned bus; + device_t dev; + uint8_t byte; + + dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI + /* enable cf9 */ + byte = pci_read_config8(dev, 0x41); + byte |= (1<<6) | (1<<5); + pci_write_config8(dev, 0x41, byte); +} - /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - bus = get_sbbusn(get_sblk()); - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI), - bus); +static void enable_cf9(void) +{ + unsigned sblk = get_sblk(); + unsigned sbbusn = get_sbbusn(sblk); + unsigned sbdn = get_sbdn(sbbusn); - set_bios_reset(); + enable_cf9_x(sbbusn, sbdn); +} - /* enable cf9 */ - pci_write_config8(dev, 0x41, 0xf1); +static void hard_reset(void) +{ + set_bios_reset(); /* reset */ - outb(0x0e, 0x0cf9); + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled } static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) diff --git a/src/southbridge/amd/amd8111/amd8111_early_smbus.c b/src/southbridge/amd/amd8111/amd8111_early_smbus.c index 8ad3589e63..c8996784de 100644 --- a/src/southbridge/amd/amd8111/amd8111_early_smbus.c +++ b/src/southbridge/amd/amd8111/amd8111_early_smbus.c @@ -5,17 +5,25 @@ static void enable_smbus(void) { device_t dev; + uint8_t enable; + dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); } - uint8_t enable; - print_spew("SMBus controller enabled\r\n"); + pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); + + /* check that we can see the smbus controller I/O. */ + if (inw(SMBUS_IO_BASE)==0xFF){ + die("SMBUS controller I/O not found\n"); + } + /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); + print_spew("SMBus controller enabled\r\n"); } static int smbus_recv_byte(unsigned device) |