diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-02-03 00:26:08 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:08:35 +0200 |
| commit | 0f58d0b941559c627153943891737cf8fb0a7430 (patch) | |
| tree | 8c7dbc6c3ca44ef42bc57bc9a4f10de1659ffb8a | |
| parent | a7023904e653a0ae869d53d9fad8a56baab2d94a (diff) | |
| download | coreboot-0f58d0b941559c627153943891737cf8fb0a7430.tar.xz | |
urara: Reduce MIPS PLL jitter
The current MIPS PLL is configured in such a way that there is
excessive jitter. Correct this by applying new PLL settings. The
resultant frequency is 546MHz instead of 550MHz.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board as part of the JTAG
loading script;
BRANCH=none
Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0
Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/245620
Original-Reviewed-by: James Hartley <james.hartley@imgtec.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/mainboard/google/urara/bootblock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/urara/bootblock.c b/src/mainboard/google/urara/bootblock.c index b21a8885f4..f8f62f7031 100644 --- a/src/mainboard/google/urara/bootblock.c +++ b/src/mainboard/google/urara/bootblock.c @@ -111,7 +111,7 @@ static int init_clocks(void) /* The same frequency will be the input frequency for the SPFI block */ system_clk_setup(1); - /* MIPS CPU dividers: division by 1 -> 550 MHz + /* MIPS CPU dividers: division by 1 -> 546 MHz * This is set up as we cannot make any assumption about * the values set or not by the boot ROM code */ mips_clk_setup(0, 0); @@ -135,8 +135,8 @@ static int init_clocks(void) ret = sys_pll_setup(2, 1); if (ret != CLOCKS_OK) return ret; - /* Setup MIPS PLL at 550 MHz */ - ret = mips_pll_setup(2, 1, 13, 275); + /* Setup MIPS PLL at 546 MHz */ + ret = mips_pll_setup(2, 1, 1, 21); if (ret != CLOCKS_OK) return ret; return CLOCKS_OK; |