mb/intel/wtm2: Drop unsupported native graphics init

Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.

Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

5 files changed, 0 insertions, 482 deletions

diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig
index 76ed4bfaf2..45a8666fd7 100644
--- a/src/mainboard/intel/wtm2/Kconfig
+++ b/src/mainboard/intel/wtm2/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_SMI_HANDLER
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LPC_TPM
-	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select INTEL_INT15
 
 config CHROMEOS
diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc
index f1cf2594fc..16137462c9 100644
--- a/src/mainboard/intel/wtm2/Makefile.inc
+++ b/src/mainboard/intel/wtm2/Makefile.inc
@@ -15,9 +15,6 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
 
 romstage-y += pei_data.c
 ramstage-y += pei_data.c
diff --git a/src/mainboard/intel/wtm2/graphics.c b/src/mainboard/intel/wtm2/graphics.c
deleted file mode 100644
index 46f8ff41e3..0000000000
--- a/src/mainboard/intel/wtm2/graphics.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
-* This file is part of the coreboot project.
-*
-* Copyright 2013 Google Inc.
-*
-* This program is free software; you can redistribute it and/or modify
-* it under the terms of the GNU General Public License as published by
-* the Free Software Foundation; version 2 of the License.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-/* this file was for the most part machine generated, and in future
- * will be all machine generated. Avoid editing.
- */
-#include <console/console.h>
-#include <drivers/intel/gma/i915.h>
-
-void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
-{
-
-	io_i915_write32(0x80000000,0x45400);
-	io_i915_write32(0x00000000,_CURACNTR);
-	io_i915_write32((/* PIPEA */0x0 << 24)|0x00000000,_DSPACNTR);
-	io_i915_write32(0x00000000,_DSPBCNTR);
-	io_i915_write32(0x80000000,CPU_VGACNTRL);
-	io_i915_write32(0x00000000,_DSPASIZE+0xc);
-	io_i915_write32(0x00000000,_DSPBSURF);
-	io_i915_write32(0x00000000,0x4f050);
-	io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
-		DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
-		DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
-		DP_SYNC_VS_HIGH |0x00000091,DP_A);
-	io_i915_write32(0x00200090,_FDI_RXA_MISC);
-	io_i915_write32(0x0a000000,_FDI_RXA_MISC);
-	/* not yet documented anywhere that we can find. */
-	io_i915_write32(0x00000070,0x46408);
-	io_i915_write32(0x04000000,0x42090);
-	io_i915_write32(0x40000000,0x4f050);
-	io_i915_write32(0x00000000,0x9840);
-	io_i915_write32(0xa4000000,0x42090);
-	io_i915_write32(0x00004000,0x42080);
-	io_i915_write32(0x00ffffff,0x64f80);
-	io_i915_write32(0x0007000e,0x64f84);
-	io_i915_write32(0x00d75fff,0x64f88);
-	io_i915_write32(0x000f000a,0x64f8c);
-	io_i915_write32(0x00c30fff,0x64f90);
-	io_i915_write32(0x00060006,0x64f94);
-	io_i915_write32(0x00aaafff,0x64f98);
-	io_i915_write32(0x001e0000,0x64f9c);
-	io_i915_write32(0x00ffffff,0x64fa0);
-	io_i915_write32(0x000f000a,0x64fa4);
-	io_i915_write32(0x00d75fff,0x64fa8);
-	io_i915_write32(0x00160004,0x64fac);
-	io_i915_write32(0x00c30fff,0x64fb0);
-	io_i915_write32(0x001e0000,0x64fb4);
-	io_i915_write32(0x00ffffff,0x64fb8);
-	io_i915_write32(0x00060006,0x64fbc);
-	io_i915_write32(0x00d75fff,0x64fc0);
-	io_i915_write32(0x001e0000,0x64fc4);
-	io_i915_write32(0x00ffffff,0x64e00);
-	io_i915_write32(0x0006000e,0x64e04);
-	io_i915_write32(0x00d75fff,0x64e08);
-	io_i915_write32(0x0005000a,0x64e0c);
-	io_i915_write32(0x00c30fff,0x64e10);
-	io_i915_write32(0x00040006,0x64e14);
-	io_i915_write32(0x80aaafff,0x64e18);
-	io_i915_write32(0x000b0000,0x64e1c);
-	io_i915_write32(0x00ffffff,0x64e20);
-	io_i915_write32(0x0005000a,0x64e24);
-	io_i915_write32(0x00d75fff,0x64e28);
-	io_i915_write32(0x000c0004,0x64e2c);
-	io_i915_write32(0x80c30fff,0x64e30);
-	io_i915_write32(0x000b0000,0x64e34);
-	io_i915_write32(0x00ffffff,0x64e38);
-	io_i915_write32(0x00040006,0x64e3c);
-	io_i915_write32(0x80d75fff,0x64e40);
-	io_i915_write32(0x000b0000,0x64e44);
-	/* end not yet documented. */
-	io_i915_write32(0x10000000,SDEISR+0x30);
-}
diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c
deleted file mode 100644
index 72273f8333..0000000000
--- a/src/mainboard/intel/wtm2/i915.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <stdlib.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#include <delay.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <boot/coreboot_tables.h>
-#include <smbios.h>
-#include <device/pci.h>
-#include <ec/google/chromeec/ec.h>
-
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <edid.h>
-#include <drivers/intel/gma/i915.h>
-
-/* how many bytes do we need for the framebuffer?
- * Well, this gets messy. To get an exact answer, we have
- * to ask the panel, but we'd rather zero the memory
- * and set up the gtt while the panel powers up. So,
- * we take a reasonable guess, secure in the knowledge that the
- * MRC has to overestimate the number of bytes used.
- * 8 MiB is a very safe guess. There may be a better way later, but
- * fact is, the initial framebuffer is only very temporary. And taking
- * a little long is ok; this is done much faster than the AUX
- * channel is ready for IO.
- */
-#define FRAME_BUFFER_BYTES (8*MiB)
-/* how many 4096-byte pages do we need for the framebuffer?
- * There are hard ways to get this, and easy ways:
- * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
- * on this chip (and in fact every Intel graphics chip we've seen).
- */
-#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
-
-static int verbose = 0;
-
-static unsigned int *mmio;
-static unsigned int graphics;
-static unsigned short addrport;
-static unsigned short dataport;
-static unsigned int physbase;
-
-const u32 link_edid_data[] = {
-	0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
-	0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
-	0x00545017, 0x01010000, 0x01010101, 0x01010101,
-	0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
-	0xb510003a, 0x19000010, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
-	0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
-	0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
-};
-
-static int ioread = 0, iowrite = 0;
-
-static char *regname(unsigned long addr)
-{
-	static char name[16];
-	snprintf(name, sizeof(name), "0x%lx", addr);
-	return name;
-}
-
-unsigned long io_i915_read32(unsigned long addr)
-{
-	unsigned long val;
-	outl(addr, addrport);
-	val = inl(dataport);
-	ioread += 2;
-	if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
-	return val;
-}
-
-void io_i915_write32(unsigned long val, unsigned long addr)
-{
-	if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
-	outl(addr, addrport);
-	outl(val, dataport);
-	iowrite += 2;
-}
-
-/* GTT is the Global Translation Table for the graphics pipeline.
- * It is used to translate graphics addresses to physical
- * memory addresses. As in the CPU, GTTs map 4K pages.
- * The setgtt function adds a further bit of flexibility:
- * it allows you to set a range (the first two parameters) to point
- * to a physical address (third parameter);the physical address is
- * incremented by a count (fourth parameter) for each GTT in the
- * range.
- * Why do it this way? For ultrafast startup,
- * we can point all the GTT entries to point to one page,
- * and set that page to 0s:
- * memset(physbase, 0, 4096);
- * setgtt(0, 4250, physbase, 0);
- * this takes about 2 ms, and is a win because zeroing
- * the page takes a up to 200 ms.
- * This call sets the GTT to point to a linear range of pages
- * starting at physbase.
- */
-
-static void
-setgtt(int start, int end, unsigned long base, int inc)
-{
-	int i;
-
-	for(i = start; i < end; i++){
-		u32 word = base + i*inc;
-		io_i915_write32(word|1,(i*4)|1);
-	}
-}
-
-static unsigned long tickspermicrosecond = 1795;
-static unsigned long long globalstart;
-
-static unsigned long
-microseconds(unsigned long long start, unsigned long long end)
-{
-	unsigned long ret;
-	ret = ((end - start)/tickspermicrosecond);
-	return ret;
-}
-
-static unsigned long globalmicroseconds(void)
-{
-	return microseconds(globalstart, rdtscll());
-}
-
-static int i915_init_done = 0;
-
-int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
-		unsigned int gfx);
-
-int i915lightup(unsigned int pphysbase, unsigned int piobase,
-		unsigned int pmmio, unsigned int pgfx)
-{
-	int must_cycle_power = 0;
-
-	/* frame buffer pointer */
-	u32 *l;
-	int i;
-	unsigned long before_gtt, after_gtt;
-
-	mmio = (void *)pmmio;
-	addrport = piobase;
-	dataport = addrport + 4;
-	physbase = pphysbase;
-	graphics = pgfx;
-	printk(BIOS_SPEW,
-	       "i915lightup: graphics %p mmio %p"
-	       "addrport %04x physbase %08x\n",
-	       (void *)graphics, mmio, addrport, physbase);
-	globalstart = rdtscll();
-
-	/* turn it on. The VBIOS does it this way, so we hope that's ok. */
-	verbose = 0;
-	io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
-
-	/* the AUX channel needs a small amount of time to spin up.
-	 * Rather than udelay, do some useful work:
-	 * Zero out the frame buffer memory,
-	 * and set the global translation table (GTT)
-	 */
-	printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
-	       FRAME_BUFFER_BYTES/sizeof(u32));
-	for(l = (u32 *)graphics, i = 0;
-		i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
-		l[i] = 0x1122ff;
-	}
-	printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
-				FRAME_BUFFER_PAGES, (void *)physbase);
-	before_gtt = globalmicroseconds();
-	setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
-	after_gtt = globalmicroseconds();
-
-	/* The reset is basically harmless, and can be
-	 * repeated by the VBIOS in any event.
-	 */
-
-	graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
-
-	/* failures after this point can return without
-	 * powering off the panel.
-	 */
-
-	if (1)
-		goto fail;
-	/* failures after this point MUST power off the panel
-	 * and wait 600 ms.
-	 */
-
-	i915_init_done = 1;
-	return i915_init_done;
-
-fail:
-	printk(BIOS_SPEW, "Graphics could not be started;");
-	if (must_cycle_power){
-		printk(BIOS_SPEW, "Turn off power and wait ...");
-		io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
-		udelay(600000);
-	}
-	printk(BIOS_SPEW, "Returning.\n");
-	return 0;
-
-}
diff --git a/src/mainboard/intel/wtm2/intel_dp.c b/src/mainboard/intel/wtm2/intel_dp.c
deleted file mode 100644
index b38994622f..0000000000
--- a/src/mainboard/intel/wtm2/intel_dp.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2013 Google Inc.
- * Copyright © 2008 Intel Corporation
- *
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Keith Packard <keithp@keithp.com>
- *
- */
-
-#include <console/console.h>
-#include <stdint.h>
-#include <delay.h>
-#include <drivers/intel/gma/i915.h>
-
-u32
-pack_aux(u32 *src32, int src_bytes)
-{
-	u8 *src = (u8 *)src32;
-	int	i;
-	u32 v = 0;
-
-	if (src_bytes > 4)
-		src_bytes = 4;
-	for (i = 0; i < src_bytes; i++)
-		v |= ((u32) src[i]) << ((3-i) * 8);
-	return v;
-}
-
-void
-unpack_aux(u32 src, u8 *dst, int dst_bytes)
-{
-
-	int i;
-	if (dst_bytes > 4)
-		dst_bytes = 4;
-	for (i = 0; i < dst_bytes; i++)
-		dst[i] = src >> ((3-i) * 8);
-}
-
-int
-intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
-		u8 *recv, int recv_size)
-{
-	int i;
-	int recv_bytes;
-	u32 status;
-	u32 aux_clock_divider;
-	int try, precharge = 5;
-
-	/* The clock divider is based off the hrawclk,
-	 * and would like to run at 2MHz. So, take the
-	 * hrawclk value and divide by 2 and use that
-	 *
-	 * Note that PCH attached eDP panels should use a 125MHz input
-	 * clock divider.
-	 */
-	/* 200 on link */
-	aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
-
-	/* Try to wait for any previous AUX channel activity */
-	for (try = 0; try < 3; try++) {
-		status = io_i915_read32(ch_ctl);
-		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
-			break;
-		udelay(1000);
-	}
-
-	if (try == 3) {
-	  printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
-	  status = io_i915_read32(ch_ctl);
-	  printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08x\n",
-		 status);
-	  return -1;
-	}
-
-	/* Must try at least 3 times according to DP spec */
-	for (try = 0; try < 5; try++) {
-		/* Load the send data into the aux channel data registers */
-		for (i = 0; i < send_bytes; i += 4)
-			io_i915_write32(send[i], ch_data + i);
-
-		/* Send the command and wait for it to complete */
-		io_i915_write32(
-			   DP_AUX_CH_CTL_SEND_BUSY |
-			   DP_AUX_CH_CTL_TIME_OUT_400us |
-			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
-			   DP_AUX_CH_CTL_DONE |
-			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
-			   DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
-		for (;;) {
-			status = io_i915_read32(ch_ctl);
-			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
-				break;
-			udelay(100);
-		}
-
-		/* Clear done status and any errors */
-		io_i915_write32(
-			   status |
-			   DP_AUX_CH_CTL_DONE |
-			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
-			   DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
-
-		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
-			      DP_AUX_CH_CTL_RECEIVE_ERROR))
-			continue;
-		if (status & DP_AUX_CH_CTL_DONE)
-			break;
-	}
-
-	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
-		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
-		printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
-		return -1;
-	}
-
-	/* Check for timeout or receive error.
-	 * Timeouts occur when the sink is not connected
-	 */
-	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
-		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
-		printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
-		return -1;
-	}
-
-	/* Timeouts occur when the device isn't connected, so they're
-	 * "normal" -- don't fill the kernel log with these */
-	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
-		printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
-		printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
-		return -1;
-	}
-
-	/* Unload any bytes sent back from the other side */
-	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
-		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-	if (recv_bytes > recv_size)
-		recv_bytes = recv_size;
-
-	for (i = 0; i < recv_bytes; i += 4)
-		unpack_aux(io_i915_read32(ch_data + i),
-			   recv + i, recv_bytes - i);
-
-	return recv_bytes;
-}