diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-08-05 17:36:36 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:19:49 +0200 |
| commit | 21df8d950bebb7826926071b3d123199f004b125 (patch) | |
| tree | c98b34fad7f8719f44247c8e5f92c463e2e11c34 | |
| parent | ccb01f72453f904d6ddf994321bb40ae42276296 (diff) | |
| download | coreboot-21df8d950bebb7826926071b3d123199f004b125.tar.xz | |
kunimitsu sklrvp: remove unused IedSize
The skylake code is using IED_REGION_SIZE instead of
devicetree.cb. Drop the the option from the device trees.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=None
Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290932
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11200
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/sklrvp/devicetree.cb | 3 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 9b0ca0ff78..7f1b35f438 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "gpe0_en_4" = "0x00000000" # Memory related - register "IedSize" = "0x0" register "ProbelessTrace" = "0" # Lan diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb index 66c1f18a87..128c22261b 100644 --- a/src/mainboard/intel/sklrvp/devicetree.cb +++ b/src/mainboard/intel/sklrvp/devicetree.cb @@ -68,9 +68,6 @@ chip soc/intel/skylake # Enable S0ix register "s0ix_enable" = "0" - # Memory related - register "IedSize" = "0x0" - # Probeless Trace function register "ProbelessTrace" = "0" |