soc/intel/broadwell: Fix spacing issues detected by checkpatch

Fix the following errors and warnings detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: spaces required around that '>=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required before the open parenthesis '('
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line

False positives are generated for the following test:
WARNING: space prohibited between function name and open parenthesis '('
in both pei_data.h and pei_wrapper.h

TEST=None

Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18872
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

21 files changed, 110 insertions, 110 deletions

diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index fb68ea09ca..6d20259c13 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -74,12 +74,12 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = {
 	[C_STATE_C1] = {
 		.latency = 0,
 		.power = 1000,
-		.resource = MWAIT_RES(0,0),
+		.resource = MWAIT_RES(0, 0),
 	},
 	[C_STATE_C1E] = {
 		.latency = 0,
 		.power = 1000,
-		.resource = MWAIT_RES(0,1),
+		.resource = MWAIT_RES(0, 1),
 	},
 	[C_STATE_C3] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
@@ -185,7 +185,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
 #endif
 }
 
-void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+void acpi_create_intel_hpet(acpi_hpet_t *hpet)
 {
 	acpi_header_t *header = &(hpet->header);
 	acpi_addr_t *addr = &(hpet->addr);
@@ -543,28 +543,28 @@ void generate_cpu_entries(device_t device)
 	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
 	       numcpus, cores_per_package);
 
-	for (cpuID=1; cpuID <=numcpus; cpuID++) {
-		for (coreID=1; coreID<=cores_per_package; coreID++) {
-			if (coreID>1) {
+	for (cpuID = 1; cpuID <= numcpus; cpuID++) {
+		for (coreID = 1; coreID <= cores_per_package; coreID++) {
+			if (coreID > 1) {
 				pcontrol_blk = 0;
 				plen = 0;
 			}
 
 			/* Generate processor \_PR.CPUx */
 			acpigen_write_processor(
-				(cpuID-1)*cores_per_package+coreID-1,
+				(cpuID - 1) * cores_per_package+coreID - 1,
 				pcontrol_blk, plen);
 
 			/* Generate P-state tables */
 			generate_P_state_entries(
-				coreID-1, cores_per_package);
+				coreID - 1, cores_per_package);
 
 			/* Generate C-state tables */
 			generate_C_state_entries();
 
 			/* Generate T-state tables */
 			generate_T_state_entries(
-				cpuID-1, cores_per_package);
+				cpuID - 1, cores_per_package);
 
 			acpigen_pop_len();
 		}
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 09fe5ac99c..cc26c752bb 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -270,7 +270,7 @@ static void configure_pch_power_sharing(void)
 	pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
 
 	printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
-               pch_power, pch_power_ext);
+		pch_power, pch_power_ext);
 
 	pmsync = RCBA32(PMSYNC_CONFIG);
 	pmsync2 = RCBA32(PMSYNC_CONFIG2);
@@ -434,19 +434,19 @@ static void configure_c_states(void)
 	/* C-state Interrupt Response Latency Control 3 - package C8 */
 	msr.hi = 0;
 	msr.lo = IRTL_VALID | IRTL_1024_NS |
-	         C_STATE_LATENCY_CONTROL_3_LIMIT;
+		C_STATE_LATENCY_CONTROL_3_LIMIT;
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 
 	/* C-state Interrupt Response Latency Control 4 - package C9 */
 	msr.hi = 0;
 	msr.lo = IRTL_VALID | IRTL_1024_NS |
-	         C_STATE_LATENCY_CONTROL_4_LIMIT;
+		C_STATE_LATENCY_CONTROL_4_LIMIT;
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 
 	/* C-state Interrupt Response Latency Control 5 - package C10 */
 	msr.hi = 0;
 	msr.lo = IRTL_VALID | IRTL_1024_NS |
-	         C_STATE_LATENCY_CONTROL_5_LIMIT;
+		C_STATE_LATENCY_CONTROL_5_LIMIT;
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
@@ -472,7 +472,7 @@ static void configure_misc(void)
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);
 
diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h
index 9a9e0f4437..4755ba424e 100644
--- a/src/soc/intel/broadwell/include/soc/cpu.h
+++ b/src/soc/intel/broadwell/include/soc/cpu.h
@@ -49,7 +49,7 @@
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \
 	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
-	                              (IRTL_1024_NS >> 10))
+					(IRTL_1024_NS >> 10))
 
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
index db68b464d3..0d0ad7b3d4 100644
--- a/src/soc/intel/broadwell/include/soc/me.h
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -363,7 +363,7 @@ typedef enum {
 typedef  struct {
 	u32  mbp_size	 : 8;
 	u32  num_entries : 8;
-	u32  rsvd      	 : 16;
+	u32  rsvd	 : 16;
 } __attribute__ ((packed)) mbp_header;
 
 typedef struct {
@@ -448,8 +448,8 @@ typedef struct {
 typedef struct {
 	u16  lock_state		     : 1;
 	u16  authenticate_module     : 1;
-	u16  s3authentication  	     : 1;
-	u16  flash_wear_out          : 1;
+	u16  s3authentication	     : 1;
+	u16  flash_wear_out	     : 1;
 	u16  flash_variable_security : 1;
 	u16  reserved		     : 11;
 } __attribute__ ((packed)) tdt_state_flag;
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index b66b549c20..41ce17c10b 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -37,7 +37,7 @@
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
 #define MSR_TURBO_RATIO_LIMIT		0x1ad
 #define MSR_TEMPERATURE_TARGET		0x1a2
-#define IA32_PERF_CTL 			0x199
+#define IA32_PERF_CTL			0x199
 #define IA32_THERM_INTERRUPT		0x19b
 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
 #define  ENERGY_POLICY_PERFORMANCE	0
@@ -49,9 +49,9 @@
 #define IA32_PLATFORM_DCA_CAP		0x1f8
 #define MSR_POWER_CTL			0x1fc
 #define MSR_LT_LOCK_MEMORY		0x2e7
-#define UNCORE_EMRRphysBase_MSR 	0x2f4
-#define UNCORE_EMRRphysMask_MSR 	0x2f5
-#define IA32_MC0_STATUS 		0x401
+#define UNCORE_EMRRphysBase_MSR		0x2f4
+#define UNCORE_EMRRphysMask_MSR		0x2f5
+#define IA32_MC0_STATUS			0x401
 #define SMM_FEATURE_CONTROL_MSR		0x4e0
 #define  SMM_CPU_SAVE_EN		(1 << 1)
 
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
index 1b06ac65ac..59c64ce6c5 100644
--- a/src/soc/intel/broadwell/include/soc/pci_devs.h
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -17,17 +17,17 @@
 #define _BROADWELL_PCI_DEVS_H_
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEVFN(slot,func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+#define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
 
 #if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
 #include <arch/io.h>
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEV(slot,func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
 #else
 #include <device/device.h>
 #include <device/pci_def.h>
 #define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot,func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
 #endif
 
 /* System Agent Devices */
diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h
index 4871c8efc4..577815cd7d 100644
--- a/src/soc/intel/broadwell/include/soc/rcba.h
+++ b/src/soc/intel/broadwell/include/soc/rcba.h
@@ -23,7 +23,7 @@
 #define RCBA32(x)	*((volatile u32 *)(RCBA_BASE_ADDRESS + x))
 
 #define RCBA_AND_OR(bits, x, and, or) \
-        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+	RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
 #define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
 #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
@@ -35,9 +35,9 @@
 /* Root Port configuration space hide */
 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
-#define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
+#define RPFN_FNGET(reg, port)   (((reg) >> ((port) * 4)) & 7)
 /* Set the function number for a Root Port */
-#define RPFN_FNSET(port,func)   (((func) & 7) << ((port) * 4))
+#define RPFN_FNSET(port, func)  (((func) & 7) << ((port) * 4))
 /* Root Port function number mask */
 #define RPFN_FNMASK(port)       (7 << ((port) * 4))
 
@@ -135,9 +135,9 @@
 #define SOFT_RESET_CTRL 0x38f4
 #define SOFT_RESET_DATA 0x38f8
 
-#define DIR_ROUTE(a,b,c,d) \
-  (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
-  ((b) << DIR_IBR) | ((a) << DIR_IAR))
+#define DIR_ROUTE(a, b, c, d) \
+	(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+	((b) << DIR_IBR) | ((a) << DIR_IAR))
 
 #define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
index a5247c48ba..be7e24c087 100644
--- a/src/soc/intel/broadwell/include/soc/smm.h
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -47,10 +47,10 @@ struct smm_relocation_params {
  * clobbered by the arch/x86/Kconfig if they have the same name. */
 static inline int smm_region_size(void)
 {
-        /* Make it 8MiB by default. */
-        if (CONFIG_SMM_TSEG_SIZE == 0)
-                return (8 << 20);
-        return CONFIG_SMM_TSEG_SIZE;
+	/* Make it 8MiB by default. */
+	if (CONFIG_SMM_TSEG_SIZE == 0)
+		return (8 << 20);
+	return CONFIG_SMM_TSEG_SIZE;
 }
 
 void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
index fae7879fca..cf1b13526a 100644
--- a/src/soc/intel/broadwell/include/soc/xhci.h
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -41,8 +41,8 @@
 #define  XHCI_USB3_PORTSC_WDE	(1 << 26)	/* Wake on Disconnect */
 #define  XHCI_USB3_PORTSC_WOE	(1 << 27)	/* Wake on Overcurrent */
 #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
-#define  XHCI_USB3_PORTSC_LWS  	(1 << 16)	/* Link Write Strobe */
-#define  XHCI_USB3_PORTSC_PED 	(1 << 1)	/* Port Enabled/Disabled */
+#define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
+#define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
 #define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
 #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
 #define   XHCI_PLSR_DISABLED	(4 << 5)	/* Port is disabled */
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 610b9772ee..8de38bedb7 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -106,7 +106,7 @@ static void pch_pirq_init(device_t dev)
 	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
 
 	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
-		u8 int_pin=0, int_line=0;
+		u8 int_pin = 0, int_line = 0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
 			continue;
@@ -133,7 +133,7 @@ static void pch_power_options(device_t dev)
 	const char *state;
 	/* Get the chip configuration */
 	config_t *config = dev->chip_info;
-	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 
 	/* Which state do we want to goto after g3 (power restored)?
 	 * 0 == S0 Full On
@@ -475,7 +475,7 @@ static void pch_lpc_add_mmio_resources(device_t dev)
 		res->base = RCBA_BASE_ADDRESS;
 		res->size = 16 * 1024;
 		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-		             IORESOURCE_FIXED | IORESOURCE_RESERVE;
+			     IORESOURCE_FIXED | IORESOURCE_RESERVE;
 	}
 
 	/* Check LPC Memory Decode register. */
@@ -487,7 +487,7 @@ static void pch_lpc_add_mmio_resources(device_t dev)
 			res->base = reg;
 			res->size = 16 * 1024;
 			res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-			             IORESOURCE_FIXED | IORESOURCE_RESERVE;
+				     IORESOURCE_FIXED | IORESOURCE_RESERVE;
 		}
 	}
 }
@@ -591,7 +591,7 @@ static void southcluster_inject_dsdt(device_t device)
 
 	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (!gnvs) {
-		gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+		gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
 		if (gnvs)
 			memset(gnvs, 0, sizeof(*gnvs));
 	}
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 1b086ec94d..06c92c3498 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -88,7 +88,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
 	}
 }
 #else
-# define mei_dump(ptr,dword,offset,type) do {} while (0)
+# define mei_dump(ptr, dword, offset, type) do {} while (0)
 #endif
 
 /*
@@ -504,7 +504,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
 			      &cap_msg, sizeof(cap_msg)) < 0) {
 		printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
 		return -1;
-        }
+	}
 	*cap = cap_msg.caps_sku;
 	return 0;
 }
@@ -616,7 +616,7 @@ static void intel_me_finalize(device_t dev)
 	u32 reg32;
 
 	/* S3 path will have hidden this device already */
-	if (!mei_base_address || mei_base_address == (u8*) 0xfffffff0)
+	if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
 		return;
 
 	/* Make sure IO is disabled */
@@ -647,7 +647,7 @@ static int me_icc_set_clock_enables(u32 mask)
 	if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
 		printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
 		return -1;
-        } else {
+	} else {
 		printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
 	}
 
@@ -921,7 +921,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
 	}
 #endif
 
-#define ASSIGN_FIELD_PTR(field_,val_) \
+#define ASSIGN_FIELD_PTR(field_, val_) \
 	{ \
 		mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \
 		break; \
@@ -931,7 +931,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
 	for (i = 0; i < mbp->header.mbp_size - 1;) {
 		mbp_item_header *item = (void *)&mbp->data[i];
 
-		switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) {
+		switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
 		case MBP_IDENT(KERNEL, FW_VER):
 			ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
 
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 346a0db06e..43c4744945 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -37,7 +37,7 @@ static void print_status_bits(u32 status, const char *bit_names[])
 	if (!status)
 		return;
 
-	for (i=31; i>=0; i--) {
+	for (i = 31; i >= 0; i--) {
 		if (status & (1 << i)) {
 			if (bit_names[i])
 				printk(BIOS_DEBUG, "%s ", bit_names[i]);
@@ -55,7 +55,7 @@ static void print_gpio_status(u32 status, int start)
 	if (!status)
 		return;
 
-	for (i=31; i>=0; i--) {
+	for (i = 31; i >= 0; i--) {
 		if (status & (1 << i))
 			printk(BIOS_DEBUG, "GPIO%d ", start + i);
 	}
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index 9b10d47378..e4d01c2790 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -30,12 +30,12 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }
 
 void reset_system(void)
diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c
index c014426859..f251652de4 100644
--- a/src/soc/intel/broadwell/romstage/cpu.c
+++ b/src/soc/intel/broadwell/romstage/cpu.c
@@ -30,7 +30,7 @@ void set_max_freq(void)
 {
 	msr_t msr, perf_ctl, platform_info;
 
-        /* Check for configurable TDP option */
+	/* Check for configurable TDP option */
 	platform_info = rdmsr(MSR_PLATFORM_INFO);
 
 	if ((platform_info.hi >> 1) & 3) {
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 1185788ea7..10cb733e52 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -43,7 +43,7 @@
 void raminit(struct pei_data *pei_data)
 {
 	struct region_device rdev;
-	struct memory_info* mem_info;
+	struct memory_info *mem_info;
 	pei_wrapper_entry_t entry;
 	int ret;
 
@@ -99,7 +99,7 @@ void raminit(struct pei_data *pei_data)
 	/* Print the MRC version after executing the UEFI PEI stage. */
 	u32 version = MCHBAR32(MCHBAR_PEI_VERSION);
 	printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
-		version >> 24 , (version >> 16) & 0xff,
+		version >> 24, (version >> 16) & 0xff,
 		(version >> 8) & 0xff, version & 0xff);
 
 	report_memory_config();
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index e50046c4c8..fc8b37c733 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -98,7 +98,7 @@ static void report_cpu_info(void)
 	if (cpuidr.eax < 0x80000004) {
 		strcpy(cpu_string, "Platform info not available");
 	} else {
-		u32 *p = (u32*) cpu_string;
+		u32 *p = (u32 *)cpu_string;
 		for (i = 2; i <= 4 ; i++) {
 			cpuidr = cpuid(index + i);
 			*p++ = cpuidr.eax;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 849c55d3e8..7c74aa4b8a 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -38,8 +38,8 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* Entry from cache-as-ram.inc. */
-void * asmlinkage romstage_main(unsigned long bist,
-                                uint32_t tsc_low, uint32_t tsc_hi)
+asmlinkage void *romstage_main(unsigned long bist,
+				uint32_t tsc_low, uint32_t tsc_hi)
 {
 	struct romstage_params rp = {
 		.bist = bist,
diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c
index c8ffd140d8..c4a5452c20 100644
--- a/src/soc/intel/broadwell/romstage/spi.c
+++ b/src/soc/intel/broadwell/romstage/spi.c
@@ -27,7 +27,7 @@
 
 static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
 {
-	u32 *ptr32 = (u32*)buffer;
+	u32 *ptr32 = (u32 *)buffer;
 	u32 i;
 
 	/* Clear status bits */
@@ -76,13 +76,13 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
 	}
 
 	/* Read the data */
-	for (i = 0; i < size; i+=sizeof(u32)) {
+	for (i = 0; i < size; i += sizeof(u32)) {
 		if (size-i >= 4) {
 			/* reading >= dword */
 			*ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
 		} else {
 			/* reading < dword */
-			u8 j, *ptr8 = (u8*)ptr32;
+			u8 j, *ptr8 = (u8 *)ptr32;
 			u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
 			for (j = 0; j < (size-i); j++) {
 				*ptr8++ = temp & 0xff;
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index a0dd8df25e..c1092b9242 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -73,37 +73,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+				val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+				hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 /*
@@ -301,11 +301,11 @@ static void southbridge_smi_gsmi(void)
 		return;
 
 	/* Command and return value in EAX */
-	ret = (u32*)&io_smi->rax;
+	ret = (u32 *)&io_smi->rax;
 	sub_command = (u8)(*ret >> 8);
 
 	/* Parameter buffer in EBX */
-	param = (u32*)&io_smi->rbx;
+	param = (u32 *)&io_smi->rbx;
 
 	/* drivers/elog/gsmi.c */
 	*ret = gsmi_exec(sub_command, param);
@@ -473,7 +473,7 @@ static void southbridge_smi_monitor(void)
 	RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
 
 	trap_cycle = RCBA32(0x1e10);
-	for (i=16; i<20; i++) {
+	for (i = 16; i < 20; i++) {
 		if (trap_cycle & (1 << i))
 			mask |= (0xff << ((i - 16) << 2));
 	}
@@ -496,7 +496,7 @@ static void southbridge_smi_monitor(void)
 			data = RCBA32(0x1e18);
 			data &= mask;
 			// if (smi1)
-			// 	southbridge_smi_command(data);
+			//	southbridge_smi_command(data);
 			// return;
 		}
 		// Fall through to debug
@@ -504,7 +504,7 @@ static void southbridge_smi_monitor(void)
 
 	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
 	       trap_cycle & 0xfffc);
-	for (i=0; i < 4; i++)
+	for (i = 0; i < 4; i++)
 		if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 873e909c85..a7fd9ec616 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -190,7 +190,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg)
 }
 
 static void fill_in_relocation_params(device_t dev,
-                                      struct smm_relocation_params *params)
+				      struct smm_relocation_params *params)
 {
 	u32 tseg_size;
 	u32 tsegmb;
@@ -242,7 +242,7 @@ static void fill_in_relocation_params(device_t dev,
 	params->uncore_emrr_base.lo = emrr_base;
 	params->uncore_emrr_base.hi = 0;
 	params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
-	                              MTRR_PHYS_MASK_VALID;
+					MTRR_PHYS_MASK_VALID;
 	params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
 }
 
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 924b186088..f0c1ef2544 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -90,7 +90,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
  * Intel special features, but they do consume resources that need to be
  * accounted for. */
 static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
-                             u32 *len)
+			     u32 *len)
 {
 	u32 bar;
 
@@ -110,7 +110,7 @@ struct fixed_mmio_descriptor {
 	unsigned int index;
 	u32 size;
 	int (*get_resource)(device_t dev, unsigned int index,
-	                    u32 *base, u32 *size);
+			    u32 *base, u32 *size);
 	const char *description;
 };
 
@@ -140,13 +140,13 @@ static void mc_add_fixed_mmio_resources(device_t dev)
 		size = mc_fixed_resources[i].size;
 		index = mc_fixed_resources[i].index;
 		if (!mc_fixed_resources[i].get_resource(dev, index,
-		                                        &base, &size))
+							&base, &size))
 			continue;
 
 		resource = new_resource(dev, mc_fixed_resources[i].index);
 		resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-		                  IORESOURCE_STORED | IORESOURCE_RESERVE |
-		                  IORESOURCE_ASSIGNED;
+				  IORESOURCE_STORED | IORESOURCE_RESERVE |
+				  IORESOURCE_ASSIGNED;
 		resource->base = base;
 		resource->size = size;
 		printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
@@ -185,7 +185,7 @@ struct map_entry {
 };
 
 static void read_map_entry(device_t dev, struct map_entry *entry,
-                           uint64_t *result)
+			   uint64_t *result)
 {
 	uint64_t value;
 	uint64_t mask;
@@ -346,16 +346,16 @@ static void mc_add_dram_resources(device_t dev)
 	resource->base = mc_values[TSEG_REG] - dpr_size;
 	resource->size = mc_values[BGSM_REG] - resource->base;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-	                  IORESOURCE_STORED | IORESOURCE_RESERVE |
-	                  IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+			  IORESOURCE_STORED | IORESOURCE_RESERVE |
+			  IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
 
 	/* BGSM -> TOLUD */
 	resource = new_resource(dev, index++);
 	resource->base = mc_values[BGSM_REG];
 	resource->size = mc_values[TOLUD_REG] - resource->base;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
-	                  IORESOURCE_STORED | IORESOURCE_RESERVE |
-	                  IORESOURCE_ASSIGNED;
+			  IORESOURCE_STORED | IORESOURCE_RESERVE |
+			  IORESOURCE_ASSIGNED;
 
 	/* 4GiB -> TOUUD */
 	base_k = 4096 * 1024; /* 4GiB */
@@ -371,7 +371,7 @@ static void mc_add_dram_resources(device_t dev)
 	 */
 	mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
 	reserved_ram_resource(dev, index++, (0xc0000 >> 10),
-	                      (0x100000 - 0xc0000) >> 10);
+				(0x100000 - 0xc0000) >> 10);
 
 	chromeos_reserve_ram_oops(dev, index++);
 }