diff options
author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-12-14 10:00:27 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-12-18 16:52:27 +0000 |
commit | 2942db6d6d7248fb4f2a61970b7048e2c7aa8b6c (patch) | |
tree | 09d340d7f2e385ac60cfa7bff71e25cd4cf1ded7 | |
parent | ff4da93f4e2a5279622b3669b845139f02adc166 (diff) | |
download | coreboot-2942db6d6d7248fb4f2a61970b7048e2c7aa8b6c.tar.xz |
soc/amd: Move stoneyridge features out of agesawrapper
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should
it make any assumptions about the capabilities of a particular device.
Move these into stoneyridge northbridge and southbridge files.
BUG=b:70670425
TEST=Build and run Kahlee
Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r-- | src/soc/amd/common/block/include/amdblocks/agesawrapper.h | 5 | ||||
-rw-r--r-- | src/soc/amd/common/block/pi/agesawrapper.c | 27 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 14 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 28 |
4 files changed, 54 insertions, 20 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h index d16e9ff1a0..70e6830718 100644 --- a/src/soc/amd/common/block/include/amdblocks/agesawrapper.h +++ b/src/soc/amd/common/block/include/amdblocks/agesawrapper.h @@ -54,7 +54,12 @@ VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID amd_initcpuio(void); const void *agesawrapper_locate_module(const CHAR8 name[8]); +void SetFchResetParams(FCH_RESET_INTERFACE *params); void OemPostParams(AMD_POST_PARAMS *PostParams); void SetMemParams(AMD_POST_PARAMS *PostParams); +void SetFchEnvParams(FCH_INTERFACE *params); +void SetNbEnvParams(GNB_ENV_CONFIGURATION *params); +void SetFchMidParams(FCH_INTERFACE *params); +void SetNbMidParams(GNB_MID_CONFIGURATION *params); #endif /* __AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 467206e3b7..1b9bf7bacb 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -85,10 +85,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); - - AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); - AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); + SetFchResetParams(&AmdResetParams.FchInterface); timestamp_add_now(TS_AGESA_INIT_RESET_START); status = AmdInitReset(&AmdResetParams); @@ -219,14 +216,10 @@ AGESA_STATUS agesawrapper_amdinitenv(void) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - EnvParam->FchInterface.AzaliaController = AzEnable; - EnvParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - EnvParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); - EnvParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); - EnvParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3); - EnvParam->GnbEnvConfiguration.IommuSupport = FALSE; + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + SetFchEnvParams(&EnvParam->FchInterface); + SetNbEnvParams(&EnvParam->GnbEnvConfiguration); timestamp_add_now(TS_AGESA_INIT_ENV_START); status = AmdInitEnv (EnvParam); @@ -287,16 +280,10 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); - MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; - - MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; - MidParam->FchInterface.AzaliaController = AzEnable; - MidParam->FchInterface.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - MidParam->FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); - MidParam->FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); - MidParam->FchInterface.SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == 3); + MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; + SetFchMidParams(&MidParam->FchInterface); + SetNbMidParams(&MidParam->GnbMidConfiguration); timestamp_add_now(TS_AGESA_INIT_MID_START); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 90ece8e014..9d2823f329 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -30,9 +30,11 @@ #include <device/pci_ids.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include <agesa_headers.h> #include <soc/northbridge.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> +#include <soc/iomap.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -556,3 +558,15 @@ u32 map_oprom_vendev(u32 vendev) return new_vendev; } + +void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) +{ + params->IommuSupport = FALSE; +} + +void SetNbMidParams(GNB_MID_CONFIGURATION *params) +{ + /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ + params->iGpuVgaMode = 0; + params->GnbIoapicAddress = IO_APIC2_ADDR; +} diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a9081f87e0..1357257ea9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -31,6 +31,34 @@ #include <fchec.h> #include <delay.h> #include <soc/pci_devs.h> +#include <agesa_headers.h> + +static int is_sata_config(void) +{ + return !((CONFIG_STONEYRIDGE_SATA_MODE == SataNativeIde) + || (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde)); +} + +void SetFchResetParams(FCH_RESET_INTERFACE *params) +{ + params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE); + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; +} + +void SetFchEnvParams(FCH_INTERFACE *params) +{ + params->AzaliaController = AzEnable; + params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + params->SataEnable = is_sata_config(); + params->IdeEnable = !params->SataEnable; + params->SataIdeMode = (CONFIG_STONEYRIDGE_SATA_MODE == SataLegacyIde); +} + +void SetFchMidParams(FCH_INTERFACE *params) +{ + SetFchEnvParams(params); +} /* * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |