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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-01-14 17:32:20 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-25 18:38:30 +0100 |
| commit | 2a0e998ec2d1625c214bf181189bd61ce425f0ed (patch) | |
| tree | 63afdf657ec278338b437de511f943f7a72ea805 | |
| parent | 9bcc002f1e7958c7b4234ea804b5b2b4f675ea3a (diff) | |
| download | coreboot-2a0e998ec2d1625c214bf181189bd61ce425f0ed.tar.xz | |
nb/intel/pineview: Make preallocated igd memory a cmos parameter
Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18142
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 842ffa1e7a..e1cf95f298 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,6 +25,7 @@ #include <string.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> +#include <pc80/mc146818rtc.h> #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) @@ -45,7 +46,16 @@ static void early_graphics_setup(void) const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */ + + /* vram size from cmos option */ + if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) + reg8 = 0; /* 0 for 8MB */ + /* make sure no invalid setting is used */ + if (reg8 > 6) + reg8 = 0; + /* Select 1M GTT */ + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) + | ((reg8 + 3) << 4)); printk(BIOS_SPEW, "Set GFX clocks..."); reg16 = MCHBAR16(MCH_GCFGC); |