diff options
| author | John Zhao <john.zhao@intel.com> | 2020-06-18 00:25:51 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-22 12:24:20 +0000 |
| commit | 2c807ff6fe085b645d6da42a0472f2c31d19ec29 (patch) | |
| tree | cd6d483987d066cd43af153b35f567b3433a7d71 | |
| parent | 2dcca0f924f9c4aa230c27808f772623b4cea061 (diff) | |
| download | coreboot-2c807ff6fe085b645d6da42a0472f2c31d19ec29.tar.xz | |
mb/google/volteer: Disable D3Cold for TCSS along with pass through mode
The pass through mode (SW CM) RTD3 is not supported until QS platform.
D3Cold is needed to be disabled along with upstream TBT firmware
signed_TGL_HR_4C_A0_rev6_pre4_SW_CM_PM_support_ENG_VER_perst_check_fix.
This temporary patch will need to be reverted once PM RTD3 support is
validated on QS platform.
BUG=b:159050315
TEST=Verfiy PM S0ix along with upstream TBT firmware.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98ed991e4185abf1f3168e33b099e0e97c9075f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42504
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f2e427f0bb..9732aa84a4 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -159,7 +159,7 @@ chip soc/intel/tigerlake # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" + register "TcssD3ColdEnable" = "0" # DP port register "DdiPortAConfig" = "1" # eDP |