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authorStefan Reinauer <reinauer@chromium.org>2013-05-20 15:24:13 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 21:46:46 +0200
commit2d8112523aa04bca3f4d56d6ba1660082bf279b5 (patch)
treeaa1113288877954dc953113d3176703063c937e7
parent6c184d6855a11d42f9d77bc9ddb8dfeb608072b6 (diff)
downloadcoreboot-2d8112523aa04bca3f4d56d6ba1660082bf279b5.tar.xz
exynos5420: Clear the framebuffer before making it uncacheable
If we clear the framebuffer and then flush it back to memory using cache operations, the writes are going to be full cachelines at a time. If we make it uncacheable first, the writes will be serialized writes of whatever sized chunks memset uses, probably 4 bytes or less. Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3668 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/cpu/samsung/exynos5420/cpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 1d511743b2..6e360bf350 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev)
lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size);
printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase));
+ memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
+
/*
* We need to clean and invalidate the framebuffer region and disable
* caching as well. We assume that our dcache <--> memory address
@@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
"Initializing Exynos VGA, base %p\n", (void *)lcdbase);
- memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}