nb/intel/i945: Switch to POSTCAR_STAGE

Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

5 files changed, 12 insertions, 15 deletions

diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
index 7c37019194..7993294a17 100644
--- a/src/cpu/intel/socket_441/Makefile.inc
+++ b/src/cpu/intel/socket_441/Makefile.inc
@@ -8,10 +8,7 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
 postcar-y += ../car/p4-netburst/exit_car.S
-endif
+
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
index fb5902cea6..139b1bb624 100644
--- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc
+++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc
@@ -11,11 +11,7 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-ifneq ($(CONFIG_POSTCAR_STAGE),y)
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
-else
 cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
 postcar-y += ../car/p4-netburst/exit_car.S
-endif
 
 romstage-y += ../car/romstage.c
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 482f98aaa5..e04d0c3336 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -28,6 +28,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select RELOCATABLE_RAMSTAGE
 	select INTEL_EDID
 	select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+	select POSTCAR_STAGE
+	select POSTCAR_CONSOLE
 
 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
 	def_bool n
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 0e4fcfcb54..ffeabdc678 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -29,4 +29,6 @@ romstage-y += rcven.c
 
 smm-y += udelay.c
 
+postcar-y += ram_calc.c
+
 endif
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index bc5f9c8c6d..a106d117f2 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -80,9 +80,10 @@ u32 decode_igd_memory_size(const u32 gms)
 
 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
 
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
 {
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
@@ -105,8 +106,7 @@ void *setup_stack_and_mtrrs(void)
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
 
-	/* Save the number of MTRRs to setup. Return the stack location
-	 * pointing to the number of MTRRs.
-	 */
-	return postcar_commit_mtrrs(&pcf);
+	run_postcar_phase(&pcf);
+
+	/* We do not return here. */
 }