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| author | Subrata Banik <subrata.banik@intel.com> | 2017-11-09 15:00:54 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-10 16:37:32 +0000 |
| commit | 330dc10cfd956df91855593b6f33b502c6883c55 (patch) | |
| tree | 11592ea16fd8ef62d116170d450aa236c2a5c0c1 | |
| parent | cb01efcda1808aa2ccc25aacae37f6f02bd4f9a1 (diff) | |
| download | coreboot-330dc10cfd956df91855593b6f33b502c6883c55.tar.xz | |
soc/intel/apollolake: Include HECI BAR0 address inside iomap.h
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.
Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index c3eb66bef6..d4cd0952e8 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -44,6 +44,8 @@ #define SRAM_BASE_2 0xfe902000 #define SRAM_SIZE_2 (4 * KiB) +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 |