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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-08-22 19:37:15 +0200
committerRonald G. Minnich <rminnich@gmail.com>2016-08-23 23:43:56 +0200
commit3965a522c23ea50b1a861b89a8215a524caa35f7 (patch)
treec69e71c15b08c8b9ddfe60f9d11d203467dad747
parentb6648cd888f1ba8e0e81c59f296028ba831c6eae (diff)
downloadcoreboot-3965a522c23ea50b1a861b89a8215a524caa35f7.tar.xz
arch/riscv: Enable U-mode/S-mode counters (stime, etc.)
Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/arch/riscv/virtual_memory.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 98b7edca4e..fab7d90d70 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -218,4 +218,8 @@ void mstatus_init(void)
| (1 << CAUSE_FAULT_STORE)
| (1 << CAUSE_USER_ECALL)
);
+
+ /* Enable all user/supervisor-mode counters */
+ write_csr(mscounteren, 0b111);
+ write_csr(mucounteren, 0b111);
}