diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 13:22:08 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-22 14:47:54 +0000 |
| commit | 3bff419824e71e3442dd64501c00fdf295eb1649 (patch) | |
| tree | 4034ccfe09b90eae08415d16a76e8aea18ff7b49 | |
| parent | 9f75f6897825a7c9bb3bea1d9c4881e288a0da1d (diff) | |
| download | coreboot-3bff419824e71e3442dd64501c00fdf295eb1649.tar.xz | |
sb/intel/i82801ix/early_init.c: Reorder functions
Both i82801gx and i82801jx start with the LPC setup function. For some
reason this isn't reproducible, but it should not effect functionality.
Change-Id: I9d26a151757d60e56ed70181ff7aef48e229d322
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 9fe87ce3fe..e50232b238 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -6,6 +6,39 @@ #include "i82801ix.h" #include "chip.h" +void i82801ix_lpc_setup(void) +{ + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); + const struct device *dev = pcidev_on_root(0x1f, 0); + const struct southbridge_intel_i82801ix_config *config = NULL; + + /* Configure serial IRQs.*/ + pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); + /* + * Enable some common LPC IO ranges: + * - 0x2e/0x2f, 0x4e/0x4f often SuperIO + * - 0x60/0x64, 0x62/0x66 often KBC/EC + * - 0x3f0-0x3f5/0x3f7 FDD + * - 0x378-0x37f and 0x778-0x77f LPT + * - 0x2f8-0x2ff COMB + * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL + */ + pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); + pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); + + /* Set up generic decode ranges */ + if (!dev || !dev->chip_info) + return; + config = dev->chip_info; + + pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); + pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); + pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); + pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); +} + void i82801ix_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); @@ -50,36 +83,3 @@ void i82801ix_early_init(void) /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) before they get cleared. */ } - -void i82801ix_lpc_setup(void) -{ - const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); - const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_i82801ix_config *config = NULL; - - /* Configure serial IRQs.*/ - pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); - /* - * Enable some common LPC IO ranges: - * - 0x2e/0x2f, 0x4e/0x4f often SuperIO - * - 0x60/0x64, 0x62/0x66 often KBC/EC - * - 0x3f0-0x3f5/0x3f7 FDD - * - 0x378-0x37f and 0x778-0x77f LPT - * - 0x2f8-0x2ff COMB - * - 0x3f8-0x3ff COMA - * - 0x208-0x20f GAMEH - * - 0x200-0x207 GAMEL - */ - pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); - - /* Set up generic decode ranges */ - if (!dev || !dev->chip_info) - return; - config = dev->chip_info; - - pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec); - pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec); - pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec); - pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); -} |