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| author | Zheng Bao <zheng.bao@amd.com> | 2010-10-08 03:35:12 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-10-08 03:35:12 +0000 |
| commit | 3d682fe8887b2ddd6c3c7e30c13b4e2f1c59779d (patch) | |
| tree | 3915760e7ee01cd14a7813ba71fbcb72bc844133 | |
| parent | 554c052b48ac0b36503cb41b1c054a5ead7ae4b4 (diff) | |
| download | coreboot-3d682fe8887b2ddd6c3c7e30c13b4e2f1c59779d.tar.xz | |
Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctsrc.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index e761a05eb5..258be0468d 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -848,7 +848,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -863,7 +863,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 585fc31582..b11da61156 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -800,7 +800,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is 1/2 Memclock Delay * Read Position is 1/2 Memclock Delay */ @@ -814,7 +814,7 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel) { /* Initialize the DQS Positions in preparation for - * Reciever Enable Training. + * Receiver Enable Training. * Write Position is no Delay * Read Position is 1/2 Memclock Delay */ |