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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-15 14:13:30 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-17 23:30:52 +0200
commit3f0fe68c4b29dd279d0169cda715c64e3000f963 (patch)
tree820a7852f52d2b811f95d519eea84f616b877307
parent274d20a0652f45ed54834524c485f7ab59bcdf70 (diff)
downloadcoreboot-3f0fe68c4b29dd279d0169cda715c64e3000f963.tar.xz
soc/intel/quark: Perform GPIO initialization
Set the base address and enable the GPIO and legacy GPIO controllers. Call the mainboard routine to initialize the GPIO controllers. TEST=Build and run on Galileo Gen2 Change-Id: I06aed5903d6655d2a0948fb544cf9e0db68faa26 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/intel/quark/include/soc/iomap.h12
-rw-r--r--src/soc/intel/quark/romstage/romstage.c21
2 files changed, 31 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
index 31cf604844..ce92676c54 100644
--- a/src/soc/intel/quark/include/soc/iomap.h
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -24,10 +24,18 @@
/* UART MMIO */
#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
+/* I2C/GPIO Controller */
+#define I2C_GPIO_BASE_ADDRESS 0xa0020000
+
/*
* I/O port address space
*/
-#define ACPI_BASE_ADDRESS 0x1000
-#define ACPI_BASE_SIZE 0x100
+#define ACPI_BASE_ADDRESS 0x1000
+#define ACPI_BASE_SIZE 0x100
+
+#define LEGACY_GPIO_BASE_ADDRESS 0x1080
+#define LEGACY_GPIO_SIZE 0x80
+
+#define IO_ADDRESS_VALID 0x80000000
#endif /* _QUARK_IOMAP_H_ */
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 93fb24b1c9..2f16c5f37a 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -28,6 +28,22 @@
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
+#include <soc/reg_access.h>
+
+static const struct reg_script legacy_gpio_init[] = {
+ /* Temporarily enable the legacy GPIO controller */
+ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
+ | LEGACY_GPIO_BASE_ADDRESS),
+ REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
+ REG_SCRIPT_END
+};
+
+static const struct reg_script i2c_gpio_controller_init[] = {
+ /* Temporarily enable the GPIO controller */
+ REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS),
+ REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
+ REG_SCRIPT_END
+};
void car_soc_pre_console_init(void)
{
@@ -39,6 +55,11 @@ void car_soc_pre_console_init(void)
void car_soc_post_console_init(void)
{
report_platform_info();
+
+ /* Initialize the controllers */
+ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
+ reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
+ mainboard_gpio_init();
};
static struct chipset_power_state power_state CAR_GLOBAL;