src/mb/sifive/hifive-unleashed: replace fdt in maskrom

The fdt in the maskrom cannot be used to start linux. The correct fdt
is dumped by replacing the bbl of the original firmware and used in
coreboot.

Correct the mac address in fdt by reading otp

Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/31047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>

4 files changed, 763 insertions, 2 deletions

diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
index 1fdff7b068..24531787ef 100644
--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
@@ -18,6 +18,10 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_SIFIVE_FU540
 	select BOARD_ROMSIZE_KB_32768
 	select MISSING_BOARD_RESET
+	select FLATTENED_DEVICE_TREE
+
+config HEAP_SIZE
+	default 0x10000
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
index 27ddcbad87..263297eb74 100644
--- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc
+++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc
@@ -11,8 +11,20 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
-romstage-y += romstage.c
-
 bootblock-y += memlayout.ld
+
 romstage-y += memlayout.ld
+romstage-y += romstage.c
+
 ramstage-y += memlayout.ld
+ramstage-y += fixup_fdt.c
+
+
+DTB=build/hifive-unleashed.dtb
+DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts
+$(DTB): $(DTS)
+	dtc -I dts -O dtb -o $(DTB) $(DTS)
+
+cbfs-files-y += fallback/DTB
+fallback/DTB-file := $(DTB)
+fallback/DTB-type := raw
diff --git a/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
new file mode 100644
index 0000000000..ea58e02b2e
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/fixup_fdt.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/otp.h>
+#include <soc/sdram.h>
+#include <cbfs.h>
+#include <device_tree.h>
+#include <bootstate.h>
+#include <mcall.h>
+
+static void do_fixup_mac(struct device_tree_node *node)
+{
+	uint32_t serial = otp_read_serial();
+	static unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
+	if (serial != ~0) {
+		mac[5] |= (serial >>  0) & 0xff;
+		mac[4] |= (serial >>  8) & 0xff;
+		mac[3] |= (serial >> 16) & 0xff;
+	}
+	dt_add_bin_prop(node, "local-mac-address", mac, 6);
+}
+
+static void fixup_mac(struct device_tree_node *parent)
+{
+	struct device_tree_property *prop;
+	const char *name = "local-mac-address";
+
+	list_for_each(prop, parent->properties, list_node) {
+		if (!strcmp(name, prop->prop.name))
+			do_fixup_mac(parent);
+	}
+
+	struct device_tree_node *child;
+	list_for_each(child, parent->children, list_node) {
+		fixup_mac(child);
+	}
+}
+
+static void do_fixup_memory(struct device_tree_node *node)
+{
+	u64 addrs[1], sizes[1];
+	addrs[0] = 0x80000000;
+	sizes[0] = sdram_size_mb() * 1024 * 1024;
+	dt_add_reg_prop(node, addrs, sizes, 1, 2, 2);
+}
+
+
+static void fixup_memory(struct device_tree_node *parent)
+{
+	struct device_tree_property *prop;
+	const char *name = "device_type";
+	const char *value = "memory";
+
+	list_for_each(prop, parent->properties, list_node) {
+		if (!strcmp(name, prop->prop.name)) {
+			if (!strcmp(value, (char *)prop->prop.data))
+				do_fixup_memory(parent);
+		}
+	}
+
+	struct device_tree_node *child;
+	list_for_each(child, parent->children, list_node) {
+		fixup_memory(child);
+	}
+}
+
+static void fixup_fdt(void *unused)
+{
+	void *fdt_rom;
+	struct device_tree *tree;
+
+	/* load flat dt from cbfs */
+	fdt_rom = cbfs_boot_map_with_leak("fallback/DTB", CBFS_TYPE_RAW, NULL);
+
+	/* Expand DT into a tree */
+	tree = fdt_unflatten(fdt_rom);
+
+	/* fixup tree */
+	fixup_mac(tree->root);
+	fixup_memory(tree->root);
+
+	/* convert the tree to a flat dt */
+	void *dt = malloc(dt_flat_size(tree));
+	dt_flatten(tree, dt);
+
+	/* update HLS */
+	for (int i = 0; i < CONFIG_MAX_CPUS; i++)
+		OTHER_HLS(i)->fdt = dt;
+}
+
+BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, fixup_fdt, NULL);
diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts
new file mode 100644
index 0000000000..6b9bbaa399
--- /dev/null
+++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts
@@ -0,0 +1,640 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "sifive,fu540g", "sifive,fu500";
+	model = "sifive,hifive-unleashed-a00";
+
+	aliases {
+		serial0 = &L28;
+		serial1 = &L29;
+	};
+
+	chosen {
+	};
+/*
+	firmware {
+		sifive,fsbl = "YYYY-MM-DD";
+	};
+*/
+	L3: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+		L9: cpu@0 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <16384>;
+			next-level-cache = <&L24 &L0>;
+			reg = <0>;
+			riscv,isa = "rv64imac";
+			sifive,dtim = <&L8>;
+			sifive,itim = <&L7>;
+			status = "okay";
+			L10: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L12: cpu@1 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L24 &L0>;
+			reg = <1>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L11>;
+			status = "okay";
+			tlb-split;
+			L13: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L15: cpu@2 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L24 &L0>;
+			reg = <2>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L14>;
+			status = "okay";
+			tlb-split;
+			L16: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L18: cpu@3 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L24 &L0>;
+			reg = <3>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L17>;
+			status = "okay";
+			tlb-split;
+			L19: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+		L21: cpu@4 {
+			clock-frequency = <0>;
+			compatible = "sifive,rocket0", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&L24 &L0>;
+			reg = <4>;
+			riscv,isa = "rv64imafdc";
+			sifive,itim = <&L20>;
+			status = "okay";
+			tlb-split;
+			L22: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	L36: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+	L2: soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
+		ranges;
+		refclk: refclk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <33333333>;
+			clock-output-names = "xtal";
+		};
+		prci: prci@10000000 {
+			/* compatible = "sifive,ux00prci0"; */
+			compatible = "sifive,aloeprci0";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&refclk>;
+			#clock-cells = <1>;
+		};
+		tlclk: tlclk {
+			compatible = "fixed-factor-clock";
+			clocks = <&prci 0>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+		};
+		L51: cadence-gemgxl-mgmt@100a0000 {
+			compatible = "sifive,cadencegemgxlmgmt0";
+			reg = <0x0 0x100a0000 0x0 0x1000>;
+			reg-names = "control";
+			#clock-cells = <0>;
+		};
+		L35: bus-blocker@100b8000 {
+			compatible = "sifive,bus-blocker0";
+			reg = <0x0 0x100b8000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L0: cache-controller@2010000 {
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			compatible = "sifive,ccache0", "cache";
+			interrupt-parent = <&L4>;
+			interrupts = <1 2 3>;
+			next-level-cache = <&L25 &L40 &L36>;
+			reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
+			reg-names = "control", "sideband";
+		};
+		L33: cadence-ddr-mgmt@100c0000 {
+			compatible = "sifive,cadenceddrmgmt0";
+			reg = <0x0 0x100c0000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L40: chiplink@40000000 {
+			#address-cells = <2>;
+			#size-cells = <2>;
+			compatible = "sifive,chiplink", "simple-bus";
+			ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>;
+		};
+		L5: clint@2000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			reg-names = "control";
+		};
+		L6: debug-controller@0 {
+			compatible = "sifive,debug-013", "riscv,debug-013";
+			interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>;
+			reg = <0x0 0x0 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L32: dma@3000000 {
+			#dma-cells = <1>;
+			compatible = "riscv,dma0";
+			dma-channels = <4>;
+			dma-requests = <0>;
+			interrupt-parent = <&L4>;
+			interrupts = <23 24 25 26 27 28 29 30>;
+			reg = <0x0 0x3000000 0x0 0x100000>;
+			reg-names = "control";
+			riscv,dma-pools = <1>;
+		};
+		L8: dtim@1000000 {
+			compatible = "sifive,dtim0";
+			reg = <0x0 0x1000000 0x0 0x2000>;
+			reg-names = "mem";
+		};
+		L44: ememoryotp@10070000 {
+			compatible = "sifive,ememoryotp0";
+			reg = <0x0 0x10070000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L24: error-device@18000000 {
+			compatible = "sifive,error0";
+			reg = <0x0 0x18000000 0x0 0x8000000>;
+			reg-names = "mem";
+		};
+		L52: ethernet@10090000 {
+			compatible = "cdns,macb";
+			interrupt-parent = <&L4>;
+			interrupts = <53>;
+			reg = <0x0 0x10090000 0x0 0x2000>;
+			reg-names = "control";
+
+			local-mac-address = [00 00 00 00 00 00];
+			phy-mode = "gmii";
+			clock-names = "pclk", "hclk", "tx_clk";
+			clocks = <&prci 1>, <&prci 1>, <&L51>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy1: ethernet-phy@0 {
+				reg = <0>;
+				reset-gpios = <&L31 12 1>;
+			};
+		};
+		L31: gpio@10060000 {
+			compatible = "sifive,gpio0";
+			interrupt-parent = <&L4>;
+			interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
+			reg = <0x0 0x10060000 0x0 0x1000>;
+			reg-names = "control";
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+		gpio-restart {
+			compatible = "gpio-restart";
+			gpios = <&L31 10 1>;
+		};
+		L47: i2c@10030000 {
+			compatible = "sifive,i2c0", "opencores,i2c-ocores";
+			reg = <0x0 0x10030000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+
+			reg-shift = <2>;
+			reg-io-width = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* On pre-production boards only */
+/*
+			ina233-vdd_soc_core@40 {
+				compatible = "ti,pmbus";
+				reg = <0x40>;
+			};
+			ina233-vdd_ddr_soc@44 {
+				compatible = "ti,pmbus";
+				reg = <0x44>;
+			};
+			ina233-vdd_ddr_mem@45 {
+				compatible = "ti,pmbus";
+				reg = <0x45>;
+			};
+			ina233-vdd_corepll@47 {
+				compatible = "ti,pmbus";
+				reg = <0x47>;
+			};
+			ina233-vdd_otp@4a {
+				compatible = "ti,pmbus";
+				reg = <0x4a>;
+			};
+			ina233-vdd_io@4b {
+				compatible = "ti,pmbus";
+				reg = <0x4b>;
+			};
+			ina233-vdd_ddrpll@48 {
+				compatible = "ti,pmbus";
+				reg = <0x48>;
+			};
+			ina233-avdd_ddrpll@49 {
+				compatible = "ti,pmbus";
+				reg = <0x49>;
+			};
+			ina233-vdd_givdd@4c {
+				compatible = "ti,pmbus";
+				reg = <0x4c>;
+			};
+			ina233vdd_gemgxlpll@4d {
+				compatible = "ti,pmbus";
+				reg = <0x4d>;
+			};
+*/
+			/* On the tester board */
+/*
+			m24c02 {
+				compatible = "st,24c02";
+				reg = <0x51>;
+			};
+*/
+		};
+		L4: interrupt-controller@c000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>;
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <53>;
+		};
+		L7: itim@1800000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1800000 0x0 0x4000>;
+			reg-names = "mem";
+		};
+		L11: itim@1808000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1808000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L14: itim@1810000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1810000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L17: itim@1818000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1818000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L20: itim@1820000 {
+			compatible = "sifive,itim0";
+			reg = <0x0 0x1820000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L37: memory-controller@100b0000 {
+			/* compatible = "sifive,ux00ddr0"; */
+			compatible = "sifive,aloeddr0";
+			interrupt-parent = <&L4>;
+			interrupts = <31>;
+			reg = <0x0 0x100b0000 0x0 0x4000>;
+			reg-names = "control";
+		};
+		pci@2000000000 {
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			compatible = "xlnx,axi-pcie-host-1.00.a";
+			device_type = "pci";
+			interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-parent = <&L4>;
+			interrupts = <32>;
+			ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
+			reg = <0x020 0x0 0x0 0x4000000>;
+			reg-names = "control";
+			xil_pcie_intc: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+/*
+		pci@2030000000 {
+			#address-cells = <3>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			compatible = "ms-pf,axi-pcie-host";
+			device_type = "pci";
+			bus-range = <0x01 0x7f>;
+			interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-parent = <&L4>;
+			interrupts = <32>;
+			ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>;
+			reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>;
+			reg-names = "control", "apb";
+			ms_pcie_intc: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+*/
+		L53: pinctrl@10080000 {
+			compatible = "sifive,pinctrl0";
+			reg = <0x0 0x10080000 0x0 0x1000>;
+			reg-names = "control";
+		};
+		L45: pwm@10020000 {
+			compatible = "sifive,pwm0";
+			interrupt-parent = <&L4>;
+			interrupts = <42 43 44 45>;
+			reg = <0x0 0x10020000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+			sifive,approx-period = <1000000>;
+			#pwm-cells = <2>;
+		};
+		L46: pwm@10021000 {
+			compatible = "sifive,pwm0";
+			interrupt-parent = <&L4>;
+			interrupts = <46 47 48 49>;
+			reg = <0x0 0x10021000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+			sifive,approx-period = <1000000>;
+			#pwm-cells = <2>;
+		};
+		pwmleds {
+			compatible = "pwm-leds";
+			heartbeat {
+				pwms = <&L45 0 0>;
+				max-brightness = <255>;
+				linux,default-trigger = "heartbeat";
+			};
+			mtd {
+				pwms = <&L45 1 0>;
+				max-brightness = <255>;
+				linux,default-trigger = "mtd";
+			};
+			netdev {
+				pwms = <&L45 2 0>;
+				max-brightness = <255>;
+				linux,default-trigger = "netdev";
+			};
+			panic {
+				pwms = <&L45 3 0>;
+				max-brightness = <255>;
+				linux,default-trigger = "panic";
+			};
+			/* These LEDs are on the tester board */
+/*
+			testled {
+				pwms = <&L46 0 0>;
+				max-brightness = <255>;
+			};
+			green {
+				pwms = <&L46 1 0>;
+				max-brightness = <255>;
+			};
+			red {
+				pwms = <&L46 2 0>;
+				max-brightness = <255>;
+			};
+			blue {
+				pwms = <&L46 3 0>;
+				max-brightness = <255>;
+			};
+*/
+		};
+		L27: rom@1000 {
+			compatible = "sifive,modeselect0";
+			reg = <0x0 0x1000 0x0 0x1000>;
+			reg-names = "mem";
+		};
+		L26: rom@10000 {
+			compatible = "sifive,maskrom0";
+			reg = <0x0 0x10000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+		L25: rom@a000000 {
+			compatible = "ucbbar,cacheable-zero0";
+			reg = <0x0 0xa000000 0x0 0x2000000>;
+			reg-names = "mem";
+		};
+		L28: serial@10010000 {
+			compatible = "sifive,uart0";
+			interrupt-parent = <&L4>;
+			interrupts = <4>;
+			reg = <0x0 0x10010000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+		};
+		L29: serial@10011000 {
+			compatible = "sifive,uart0";
+			interrupt-parent = <&L4>;
+			interrupts = <5>;
+			reg = <0x0 0x10011000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+		};
+		L49: spi@10040000 {
+			compatible = "sifive,spi0";
+			interrupt-parent = <&L4>;
+			interrupts = <51>;
+			reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
+			reg-names = "control", "mem";
+			clocks = <&tlclk>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash@0 {
+				compatible = "issi,is25wp256d", "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+				m25p,fast-read;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+		};
+		L50: spi@10041000 {
+			compatible = "sifive,spi0";
+			interrupt-parent = <&L4>;
+			interrupts = <52>;
+			reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>;
+			reg-names = "control", "mem";
+			clocks = <&tlclk>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* These flash chips are on the tester board */
+/*
+			flash@0 {
+				compatible = "issi,is25wp032", "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <25000000>;
+				m25p,fast-read;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+			flash@1 {
+				compatible = "issi,is25wp032", "jedec,spi-nor";
+				reg = <1>;
+				spi-max-frequency = <25000000>;
+				m25p,fast-read;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+			flash@2 {
+				compatible = "issi,is25wp032", "jedec,spi-nor";
+				reg = <2>;
+				spi-max-frequency = <25000000>;
+				m25p,fast-read;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+			flash@3 {
+				compatible = "issi,is25wp032", "jedec,spi-nor";
+				reg = <3>;
+				spi-max-frequency = <25000000>;
+				m25p,fast-read;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+*/
+		};
+		L30: spi@10050000 {
+			compatible = "sifive,spi0";
+			interrupt-parent = <&L4>;
+			interrupts = <6>;
+			reg = <0x0 0x10050000 0x0 0x1000>;
+			reg-names = "control";
+			clocks = <&tlclk>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			mmc@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0>;
+				spi-max-frequency = <20000000>;
+				voltage-ranges = <3300 3300>;
+				disable-wp;
+				gpios = <&L31 11 1>;
+			};
+		};
+		L23: teststatus@4000 {
+			compatible = "sifive,test0";
+			reg = <0x0 0x4000 0x0 0x1000>;
+			reg-names = "control";
+		};
+	};
+};