cpu/intel: Use the common code to initialize the romstage timestamps

The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

37 files changed, 3 insertions, 228 deletions

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 2daf47b29b..264ad4ab7f 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -17,6 +17,7 @@
 #include <cpu/x86/mtrr.h>
 #include <arch/symbols.h>
 #include <program_loading.h>
+#include <timestamp.h>
 
 #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
 
@@ -59,6 +60,8 @@ static void romstage_main(unsigned long bist)
  */
 asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
 {
+	timestamp_init(base_timestamp);
+	timestamp_add_now(TS_START_ROMSTAGE);
 	romstage_main(bist);
 }
 #endif
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 688f3579db..ff729d6285 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -77,9 +77,6 @@ void romstage_common(const struct romstage_params *params)
 	int boot_mode;
 	int wake_from_s3;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (params->bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index fe16fdd37e..ad184a8cfc 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <halt.h>
@@ -234,9 +233,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 };
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index e5e1110591..64c313c406 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -89,9 +89,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 41e87b2a00..ba5047144c 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <console/console.h>
@@ -183,9 +182,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	u8 c_bsel = msr_get_fsb();
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c
index eb534ca03b..527f31bcb7 100644
--- a/src/mainboard/asus/p5qc/romstage.c
+++ b/src/mainboard/asus/p5qc/romstage.c
@@ -73,9 +73,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich10_enable_lpc();
 	mb_gpio_init();
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 2c1b586a4a..00ab127c67 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -146,9 +146,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
index 194bd7373e..cde813c159 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -84,9 +84,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int s3resume = 0;
 	int boot_path;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index a695c53505..3ebcce3322 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -87,9 +87,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set up southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 820a333184..471977fd9d 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -29,7 +29,6 @@
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
-#include <timestamp.h>
 #include "option_table.h"
 
 static void setup_special_ich7_gpios(void)
@@ -170,7 +169,6 @@ static void rcba_config(void)
 	/* Enable PCIe Root Port Clock Gate */
 	// RCBA32(0x341c) = 0x00000001;
 
-
 	/* This should probably go into the ACPI enable trap */
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
@@ -238,9 +236,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0;
 
-	timestamp_init(timestamp_get());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index acf57445bb..55b154927e 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <superio/ite/it8718f/it8718f.h>
 #include <superio/ite/common/ite.h>
 #include <console/console.h>
@@ -144,10 +143,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0, boot_mode = 0;
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 78be08b3ba..d3fe50c6fd 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -132,9 +132,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_gpio_init();
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 3f52f6ca28..9eaa8de57b 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -18,7 +18,6 @@
 #include <stdint.h>
 #include <halt.h>
 #include <arch/io.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/bist.h>
@@ -203,9 +202,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 8d5224e19f..8648e20de0 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -37,7 +37,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
-
 /* Early mainboard specific GPIO setup */
 static void mb_gpio_init(void)
 {
@@ -93,9 +92,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int s3resume = 0;
 	int boot_path;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 9a4e0675b6..5e3535ad2b 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -20,7 +20,6 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
-#include <timestamp.h>
 #include <superio/smsc/lpc47m15x/lpc47m15x.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
@@ -125,10 +124,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0, boot_mode = 0;
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 830bc73d75..d1bf1bd1e4 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -82,9 +82,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 36aa1498b5..aa8c50ec05 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -75,9 +75,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich10_enable_lpc();
 	mb_gpio_init();
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index e85135bfc6..f0d4903bba 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -17,7 +17,6 @@
 
 #include <stdint.h>
 #include <halt.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/bist.h>
@@ -291,10 +290,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0;
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 6d93112588..1a708ae195 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -30,7 +30,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
-#include <timestamp.h>
 #include "dock.h"
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -68,9 +67,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int err;
 	u16 reg16;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 44ac585721..9216848f06 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -168,10 +167,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index 6d0bc97f10..31de0e3e9d 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -68,9 +68,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	u8 boot_path = 0;
 	u8 s3_resume;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* Set southbridge and Super I/O GPIOs. */
 	ich7_enable_lpc();
 	mb_lpc_setup();
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 2cd1b213b0..a0a1ace16e 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -29,12 +29,10 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
-#include <timestamp.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define MCH_DEV PCI_DEV(0, 0, 0)
 
-
 static void early_lpc_setup(void)
 {
 	/* Set up SuperIO LPC forwards */
@@ -56,9 +54,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 9c5930ebb1..7b75d16444 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -166,10 +165,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int s3resume = 0;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index ed0cc7606a..985cebaa87 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
@@ -168,10 +167,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int dock_err;
 	const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 };
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 1b16266c43..0003401508 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <timestamp.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
@@ -210,10 +209,6 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	int s3resume = 0;
 
-
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 1bcfd622f0..b88671c705 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -30,7 +30,6 @@
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <superio/smsc/lpc47n227/lpc47n227.h>
-#include <timestamp.h>
 
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
@@ -107,7 +106,6 @@ static void default_superio_gpio_setup(void)
 	/* Exit configuration state. */
 	pnp_exit_conf_state(sio);
 
-
 	/* Enable decoding of 0x600-0x60f through lpc. */
 	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
 
@@ -123,9 +121,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	/* basic northbridge setup, including MMCONF BAR */
 	gm45_early_init();
 
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 7345443c3d..26f49772f8 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -53,9 +53,6 @@ void mainboard_romstage_entry(unsigned long bist)
 		halt ();
 	}
 
-	timestamp_init(get_initial_timestamp());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
 	if (bist == 0)
 		enable_lapic();
 
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85419030b4..673f0c74af 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "pch.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On Cougar Point we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 /*
  * Enable Prefetching and Caching.
  */
@@ -80,8 +68,6 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
 	set_spi_speed();
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index 3e151fcb75..a9ec9b1a2c 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -15,8 +15,6 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include "pch.h"
@@ -25,15 +23,6 @@
 #include <rules.h>
 
 #if ENV_ROMSTAGE
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 pm1_cnt;
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index c9c19a3b78..6d65df3983 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "i82801gx.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On i945/ICH7 we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -43,8 +31,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 11da3ec4b1..a52fb8512e 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -15,21 +15,10 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801gx.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index bb025b0eae..6252712eba 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,19 +14,6 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
-
-static void store_initial_timestamp(void)
-{
-	/*
-	 * We have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
 
 static void enable_spi_prefetch(void)
 {
@@ -43,6 +30,5 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
 	enable_spi_prefetch();
 }
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index 7c4dafaef6..c40f9b73ea 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,19 +15,8 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include "i82801ix.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 void i82801ix_early_init(void)
 {
 	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index 115555c599..cc685c4544 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -14,21 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "i82801jx.h"
 
-static void store_initial_timestamp(void)
-{
-	/*
-	 * We have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -44,7 +31,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c
index 74f0ee2920..a59fdccedc 100644
--- a/src/southbridge/intel/i82801jx/early_lpc.c
+++ b/src/southbridge/intel/i82801jx/early_lpc.c
@@ -15,21 +15,10 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801jx.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 1a9e7bba61..cb595cdd0c 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "pch.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On Cougar Point we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 /*
  * Enable Prefetching and Caching.
  */
@@ -83,8 +71,6 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	map_rcba();
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 46e803d82f..912df8ea4c 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -18,8 +18,6 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <elog.h>
 #include "pch.h"
 #include "chip.h"
@@ -68,15 +66,6 @@ static void pch_generic_setup(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 static int sleep_type_s3(void)
 {
 	u32 pm1_cnt;