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authorMarc Jones <marc.jones@scarletltd.com>2018-04-25 16:43:18 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-04-27 09:13:31 +0000
commit4c887eaebae579ccf3cd95abd976911b4a238ce6 (patch)
treed353188750844963b85ca022c659b4b78f8f15d6
parent99fe7d243df0a234a96ae7b0febd827d773ab33a (diff)
downloadcoreboot-4c887eaebae579ccf3cd95abd976911b4a238ce6.tar.xz
soc/amd/stoneyridge: Enable CMOS VBNV backup to flash
Now that we have SPI flash writes working, we can support VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve the area in FMAP. BUG=b:77347873 TEST=Manually clear CMOS and check coreboot restores VBNV from flash. Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25842 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/stoneyridge/Kconfig3
-rw-r--r--src/soc/amd/stoneyridge/Makefile.inc3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index e723296ae4..f544796aab 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS
select C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CONSOLE
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select RELOCATABLE_MODULES
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select PARALLEL_MP
@@ -72,6 +73,8 @@ config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+ select VBOOT_VBNV_CMOS
+ select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config UDELAY_LAPIC_FIXED_FSB
int
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 31dc439397..54b1198b32 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -49,6 +49,7 @@ bootblock-y += sb_util.c
bootblock-y += tsc_freq.c
bootblock-y += southbridge.c
bootblock-y += nb_util.c
+bootblock-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += BiosCallOuts.c
romstage-y += i2c.c
@@ -67,6 +68,7 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
romstage-y += tsc_freq.c
romstage-y += southbridge.c
romstage-y += nb_util.c
+romstage-$(CONFIG_SPI_FLASH) += spi.c
verstage-y += gpio.c
verstage-y += i2c.c
@@ -77,6 +79,7 @@ verstage-y += reset.c
verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
verstage-y += tsc_freq.c
verstage-y += nb_util.c
+verstage-$(CONFIG_SPI_FLASH) += spi.c
postcar-y += monotonic_timer.c
postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c