Trivial. Spell checking.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 37 insertions, 44 deletions

diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 167088f200..87ac3acf36 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -61,7 +61,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
  * guarantee that the NB scrubs the entire dram on its node. Do do this, we
  * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR
  * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all
- * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do
+ * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do
  * this efficiently, we need only to sample one of the nodes, the node with the
  * largest ammount of dram populated is the one which will take the longest amount
  * of time (the scrub rate is set to max, the same rate, on all nodes).  So,
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index 64500f0d58..bc8e944328 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -38,7 +38,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	u32 lo, hi;
 
 	/* Set temporary top of memory from Node structure data.
-	 * Adjust temp top of memory down to accomodate 32-bit IO space.
+	 * Adjust temp top of memory down to accommodate 32-bit IO space.
 	 * Bottom40bIO=top of memory, right justified 8 bits
 	 * 	(defines dram versus IO space type)
 	 * Bottom32bIO=sub 4GB top of memory, right justified 8 bits
@@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
 	 * 2. Each range must be naturally aligned (Base is same as size)
 	 *
 	 * There are two code paths: the ascending path and descending path
-	 * (analogous to bsf and bsr), where the next limit is a funtion of the
+	 * (analogous to bsf and bsr), where the next limit is a function of the
 	 * next set bit in a forward or backward sequence of bits (as a function
 	 * of the Limit). We start with the ascending path, to ensure that
 	 * regions are naturally aligned, then we switch to the descending path
@@ -219,7 +219,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
 	u32 lo, hi;
 
 	/*======================================================================
-	 * Adjust temp top of memory down to accomodate UMA memory start
+	 * Adjust temp top of memory down to accommodate UMA memory start
 	 *======================================================================*/
 	/* Bottom32bIO=sub 4GB top of memory, right justified 8 bits
 	 * (defines dram versus IO space type)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 288093c73b..ca03f4b5ac 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -56,7 +56,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
  * guarantee that the NB scrubs the entire dram on its node. Do do this, we
  * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR
  * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all
- * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do
+ * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do
  * this efficiently, we need only to sample one of the nodes, the node with the
  * largest ammount of dram populated is the one which will take the longest amount
  * of time (the scrub rate is set to max, the same rate, on all nodes).  So,
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index 947da43ef2..8812dd9bd7 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -36,7 +36,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	u32 lo, hi;
 
 	/* Set temporary top of memory from Node structure data.
-	 * Adjust temp top of memory down to accomodate 32-bit IO space.
+	 * Adjust temp top of memory down to accommodate 32-bit IO space.
 	 * Bottom40bIO=top of memory, right justified 8 bits
 	 * 	(defines dram versus IO space type)
 	 * Bottom32bIO=sub 4GB top of memory, right justified 8 bits
@@ -145,7 +145,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
 	 * 2. Each range must be naturally aligned (Base is same as size)
 	 *
 	 * There are two code paths: the ascending path and descending path
-	 * (analogous to bsf and bsr), where the next limit is a funtion of the
+	 * (analogous to bsf and bsr), where the next limit is a function of the
 	 * next set bit in a forward or backward sequence of bits (as a function
 	 * of the Limit). We start with the ascending path, to ensure that
 	 * regions are naturally aligned, then we switch to the descending path
@@ -213,7 +213,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
 	u32 lo, hi;
 
 	/*======================================================================
-	 * Adjust temp top of memory down to accomodate UMA memory start
+	 * Adjust temp top of memory down to accommodate UMA memory start
 	 *======================================================================*/
 	/* Bottom32bIO=sub 4GB top of memory, right justified 8 bits
 	 * (defines dram versus IO space type)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index fdc35e3bfb..d46a4c6199 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -91,7 +91,7 @@ void AgesaHwWlPhase1(sMCTStruct *pMCTData, sDCTStruct *pDCTData,
 				DRAM_ADD_DCT_PHY_CONTROL_REG, WrtLvTrEn, WrtLvTrEn, 1);
 	else
 	{
-		/* Broadcast write to all D3Dbyte chiplet register offset 0xc
+		/* Broadcast write to all D3Dbyte chipset register offset 0xc
 		 * Set bit 0 (wrTrain)
 		 * Program bit 4 to nibble being trained (only matters for x4dimms)
 		 * retain value of 3:2 (Trdimmsel)
@@ -114,7 +114,7 @@ void AgesaHwWlPhase1(sMCTStruct *pMCTData, sDCTStruct *pDCTData,
 		AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value);
 		Value = bitTestSet(Value, 0);	/* enable WL training */
 		Value = bitTestReset(Value, 4); /* for x8 only */
-		Value = bitTestReset(Value, 5); /* for harward WL training */
+		Value = bitTestReset(Value, 5); /* for hardware WL training */
 		AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value);
 		Addr=0x4D030F0C;
 		AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr);
@@ -172,7 +172,7 @@ void AgesaHwWlPhase1(sMCTStruct *pMCTData, sDCTStruct *pDCTData,
  * Parameters:
  *	IN  OUT   *DCTData - Pointer to buffer with information about each DCT
  *	IN	u32: MRS value
- *	OUT	u32: sWAPPED BANK BITS
+ *	OUT	u32: Swapped BANK BITS
  *
  * ----------------------------------------------------------------------------
  */
@@ -208,7 +208,7 @@ u32 swapAddrBits_wl(sDCTStruct *pDCTData, u32 MRSValue)
  *   Parameters:
  *       IN  OUT   *DCTData - Pointer to buffer with information about each DCT
  *       IN	u32: MRS value
- *       OUT       u32: sWAPPED BANK BITS
+ *       OUT       u32: Swapped BANK BITS
  *
  * ----------------------------------------------------------------------------
  */
@@ -262,7 +262,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 	MemClkFreq = get_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId,
 			FUN_DCT, DRAM_CONFIG_HIGH, 0, 2);
 	/* Configure the DCT to send initialization MR commands to the target DIMM
-	 * ;by programming the F2x[1,0]7C register using the following steps.
+	 * by programming the F2x[1,0]7C register using the following steps.
 	 */
 	rank = 0;
 	while ((rank < pDCTData->DimmRanks[dimm]) && (rank < 2))
@@ -271,14 +271,14 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 		set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 			DRAM_INIT, MrsChipSelStart, MrsChipSelEnd, dimm*2+rank);
 		/* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM
-		 * ;register that defines the required DDR3-defined function for write
-		 * ; levelization.
+		 * register that defines the required DDR3-defined function for write
+		 * levelization.
 		 */
 		MrsBank = swapBankBits(pDCTData,1);
 		set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 			DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank);
 		/* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function
-		 * ; for write levelization.
+		 * for write levelization.
 		 */
 		tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0 */
 
@@ -347,7 +347,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 			tempW1 = bitTestSet(tempW, MRS_Level);
 			if (rank == 0)
 			{
-				/* ?Enable the output driver of the first rank of the target DIMM. */
+				/* Enable the output driver of the first rank of the target DIMM. */
 				tempW = tempW1;
 			}
 			else
@@ -371,7 +371,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 		set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 			DRAM_INIT, MrsAddressStart, MrsAddressEnd, tempW);
 		/* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to
-		 * ;the specified DIMM.
+		 * the specified DIMM.
 		 */
 		set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 			DRAM_INIT, SendMrsCmd, SendMrsCmd, 1);
@@ -381,13 +381,13 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 		{
 		}
 		/* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM
-		 * ;register that defines the required DDR3-defined function for Rtt_WR.
+		 * register that defines the required DDR3-defined function for Rtt_WR.
 		 */
 		MrsBank = swapBankBits(pDCTData,2);
 		set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 			DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank);
 		/* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function
-		 * ; for Rtt_WR (DRAMTermDyn).
+		 * for Rtt_WR (DRAMTermDyn).
 		 */
 		tempW = 0;/* PASR = 0,*/
 		/* program MrsAddress[7,6,5:3]=SRT,ASR,CWL,
@@ -457,19 +457,19 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 				{
 
 					/* Program F2x[1, 0]7C[MrsChipSel[2:0]] for the current rank
-					 * ;to be trained.
+					 * to be trained.
 					 */
 					set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId,
 						FUN_DCT, DRAM_INIT, MrsChipSelStart, MrsChipSelEnd, currDimm*2+rank);
 					/* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal
-					 * ;DRAM register that defines the required DDR3-defined function
-					 * ; for write levelization.
+					 * DRAM register that defines the required DDR3-defined function
+					 * for write levelization.
 					 */
 					MrsBank = swapBankBits(pDCTData,1);
 					set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId,
 						FUN_DCT, DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank);
 					/* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required
-					 * ;DDR3-defined function for write levelization.
+					 * DDR3-defined function for write levelization.
 					 */
 					tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */
 
@@ -528,7 +528,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 					set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId,
 						FUN_DCT, DRAM_INIT, MrsAddressStart, MrsAddressEnd, tempW);
 					/* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command
-					 * ; to the specified DIMM.
+					 * to the specified DIMM.
 					 */
 					set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId,
 						FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd, 1);
@@ -537,13 +537,13 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl)
 							pDCTData->NodeId, FUN_DCT, DRAM_INIT,
 							SendMrsCmd, SendMrsCmd)) == 1);
 					/* Program F2x[1, 0]7C[MrsBank[2:0]] for the appropriate internal DRAM
-					 * ;register that defines the required DDR3-defined function for Rtt_WR.
+					 * register that defines the required DDR3-defined function for Rtt_WR.
 					 */
 					MrsBank = swapBankBits(pDCTData,2);
 					set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT,
 						DRAM_INIT, MrsBankStart, MrsBankEnd, MrsBank);
 					/* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required DDR3-defined function
-					 * ; for Rtt_WR (DRAMTermDyn).
+					 * for Rtt_WR (DRAMTermDyn).
 					 */
 					tempW = 0;/* PASR = 0,*/
 					/* program MrsAddress[7,6,5:3]=SRT,ASR,CWL,
@@ -651,7 +651,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass)
 	u16 Addl_Data_Offset, Addl_Data_Port;
 
 	/* Program F2x[1, 0]9C_x08[WrLvOdt[3:0]] to the proper ODT settings for the
-	 * ;current memory subsystem configuration.
+	 * current memory subsystem configuration.
 	 */
 	programODT(pMCTData, pDCTData, dimm);
 
@@ -711,12 +711,12 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass)
 		while(ByteLane < MAX_BYTE_LANES)
 		{
 			/* Program an initialization value to registers F2x[1, 0]9C_x[51:50] and
-			 * ;F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields
-			 * ; If the target frequency is different than 400MHz, BIOS must
+			 * F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields
+			 * If the target frequency is different than 400MHz, BIOS must
 			 * execute two training passes for each DIMM.
 			 * For pass 1 at a 400MHz MEMCLK frequency, use an initial total delay value
-			 * ; of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined
-			 * ;by design.
+			 * of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined
+			 * by design.
 			 */
 			pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross;
 			pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c
index b153eef71e..c921e3dcf1 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c
@@ -64,7 +64,6 @@ static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue)
 }
 
 /*-----------------------------------------------------------------------------
- * uint 32
  * u32 bitTestSet(u32 csMask,u32 tempD)
  *
  * Description:
@@ -86,7 +85,6 @@ static u32 bitTestSet(u32 csMask,u32 tempD)
 }
 
 /*-----------------------------------------------------------------------------
- * uint 32
  * u32 bitTestReset(u32 csMask,u32 tempD)
  *
  * Description:
@@ -110,12 +108,11 @@ static u32 bitTestReset(u32 csMask,u32 tempD)
 }
 
 /*-----------------------------------------------------------------------------
- * uint 32
  *  u32 get_Bits(DCTStruct *DCTData, u8 DCT, u8 Node, u8 func, u16 offset,
  *                 u8 low, u8 high)
  *
  * Description:
- *     This routine Gets the PCT bits from the specidfied Node, DCT and PCI address
+ *     This routine Gets the PCT bits from the specified Node, DCT and PCI address
  *
  * Parameters:
  *   IN  OUT *DCTData - Pointer to buffer with information about each DCT
@@ -161,12 +158,11 @@ static u32 get_Bits(sDCTStruct *pDCTData,
 }
 
 /*-----------------------------------------------------------------------------
- * uint 32
  *  void set_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, u16 offset,
  *                u8 low, u8 high, u32 value)
  *
  * Description:
- *     This routine Sets the PCT bits from the specidfied Node, DCT and PCI address
+ *     This routine Sets the PCT bits from the specified Node, DCT and PCI address
  *
  * Parameters:
  *   IN  OUT *DCTData - Pointer to buffer with information about each DCT
@@ -212,12 +208,11 @@ static void set_Bits(sDCTStruct *pDCTData,
 }
 
 /*-------------------------------------------------
- * uint 32
  *  u32 get_ADD_DCT_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func,
  *                         u16 offset,u8 low, u8 high)
  *
  * Description:
- *     This routine gets the Additional PCT register from Function 2 by specidfied
+ *     This routine gets the Additional PCT register from Function 2 by specified
  *   Node, DCT and PCI address
  *
  * Parameters:
@@ -251,12 +246,11 @@ static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData,
 }
 
 /*-------------------------------------------------
- * uint 32
  *  void set_DCT_ADDR_Bits(DCTStruct *DCTData, u8 DCT,u8 Node,u8 func,
  *                         u16 offset,u8 low, u8 high, u32 value)
  *
  * Description:
- *     This routine sets the Additional PCT register from Function 2 by specidfied
+ *     This routine sets the Additional PCT register from Function 2 by specified
  *   Node, DCT and PCI address
  *
  * Parameters:
@@ -297,7 +291,6 @@ static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData,
 }
 
 /*-------------------------------------------------
- * uint 32
  * BOOL bitTest(u32 value, u8 bitLoc)
  *
  * Description:
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
index 9b20699224..993bd69690 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h
@@ -23,7 +23,7 @@
 #define MAX_TOTAL_DIMMS 8	/* Maximum Number of DIMMs in systems */
 				/* (DCT0 + DCT1) */
 #define MAX_DIMMS 4		/* Maximum Number of DIMMs on each DCT */
-#define MAX_LDIMMS 4		/* Maximum number of Logial DIMMs per DCT */
+#define MAX_LDIMMS 4		/* Maximum number of Logical DIMMs per DCT */
 
 /*MCT Max variables */
 #define MAX_ERRORS 32		/* Maximum number of Errors Reported */