src/sifive: Add the SiFive Freedom Unleashed 540 SoC

The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).

More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/

Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

10 files changed, 407 insertions, 0 deletions

diff --git a/src/soc/sifive/Kconfig b/src/soc/sifive/Kconfig
new file mode 100644
index 0000000000..14900be4ba
--- /dev/null
+++ b/src/soc/sifive/Kconfig
@@ -0,0 +1,2 @@
+# Load all chipsets
+source "src/soc/sifive/*/Kconfig"
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
new file mode 100644
index 0000000000..d247c280b5
--- /dev/null
+++ b/src/soc/sifive/fu540/Kconfig
@@ -0,0 +1,26 @@
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+config SOC_SIFIVE_FU540
+	bool
+	select ARCH_RISCV
+	select ARCH_BOOTBLOCK_RISCV
+	select ARCH_VERSTAGE_RISCV
+	select ARCH_ROMSTAGE_RISCV
+	select ARCH_RAMSTAGE_RISCV
+	select BOOTBLOCK_CONSOLE
+	select DRIVERS_UART_SIFIVE
+
+if SOC_SIFIVE_FU540
+
+endif
diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc
new file mode 100644
index 0000000000..8a2f3a692b
--- /dev/null
+++ b/src/soc/sifive/fu540/Makefile.inc
@@ -0,0 +1,33 @@
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+ifeq ($(CONFIG_SOC_SIFIVE_FU540),y)
+
+bootblock-y += uart.c
+bootblock-y += media.c
+bootblock-y += bootblock.c
+
+romstage-y += uart.c
+romstage-y += media.c
+
+ramstage-y += uart.c
+ramstage-y += media.c
+ramstage-y += cbmem.c
+
+CPPFLAGS_common += -Isrc/soc/sifive/fu540/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+	@printf "    GPT        $(notdir $(@))\n"
+	@util/riscv/sifive-gpt.py $< $@
+
+endif
diff --git a/src/soc/sifive/fu540/bootblock.c b/src/soc/sifive/fu540/bootblock.c
new file mode 100644
index 0000000000..203081c90c
--- /dev/null
+++ b/src/soc/sifive/fu540/bootblock.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/addressmap.h>
+
+void bootblock_soc_init(void)
+{
+	printk(BIOS_INFO, "Boot mode: %d\n", read32((uint32_t *)FU540_MSEL));
+}
diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c
new file mode 100644
index 0000000000..8648370f20
--- /dev/null
+++ b/src/soc/sifive/fu540/cbmem.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+	/* dummy value */
+	return (void *)(4ULL * GiB);
+}
diff --git a/src/soc/sifive/fu540/include/soc/addressmap.h b/src/soc/sifive/fu540/include/soc/addressmap.h
new file mode 100644
index 0000000000..904c8b6589
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/addressmap.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define FU540_MSEL		0x00001000
+#define FU540_DTIM		0x01000000
+#define FU540_L2LIM		0x08000000
+#define FU540_UART0		0x10010000
+#define FU540_UART(x)		(FU540_UART0 + 0x1000 * (x))
+#define FU540_PRCI		0x10000000
+#define FU540_QSPI0		0x10040000
+#define FU540_QSPI1		0x10041000
+#define FU540_QSPI2		0x10050000
+#define FU540_GPIO		0x10060000
+#define FU540_OTP		0x10070000
+#define FU540_PINCTRL		0x10080000
+#define FU540_ETHMAC		0x10090000
+#define FU540_ETHMGMT		0x100a0000
+#define FU540_DDRCTRL		0x100b0000
+#define FU540_DDRMGMT		0x100c0000
+#define FU540_QSPI0FLASH	0x20000000
+#define FU540_QSPI1FLASH	0x30000000
+#define FU540_DRAM		0x80000000
diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld
new file mode 100644
index 0000000000..a03c03d345
--- /dev/null
+++ b/src/soc/sifive/fu540/include/soc/memlayout.ld
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <soc/addressmap.h>
+
+#include <arch/header.ld>
+
+#define L2LIM_START(addr) SYMBOL(l2lim, addr)
+#define L2LIM_END(addr) SYMBOL(el2lim, addr)
+
+SECTIONS
+{
+	L2LIM_START(FU540_L2LIM)
+	BOOTBLOCK(FU540_L2LIM, 64K)
+	STACK(FU540_L2LIM + 64K, 4K)
+	PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)
+	ROMSTAGE(FU540_L2LIM + 128K, 128K)
+	L2LIM_END(FU540_L2LIM + 2M)
+
+	DRAM_START(FU540_DRAM)
+	RAMSTAGE(FU540_DRAM, 256K)
+}
diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c
new file mode 100644
index 0000000000..7b9ccb0e3c
--- /dev/null
+++ b/src/soc/sifive/fu540/media.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot_device.h>
+
+/* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */
+static struct mem_region_device mdev =
+	MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE);
+
+const struct region_device *boot_device_ro(void)
+{
+	return &mdev.rdev;
+}
diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c
new file mode 100644
index 0000000000..940dc97856
--- /dev/null
+++ b/src/soc/sifive/fu540/uart.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <soc/addressmap.h>
+
+uintptr_t uart_platform_base(int idx)
+{
+	if (idx < 2)
+		return FU540_UART(idx);
+	else
+		return 0;
+}
diff --git a/util/riscv/sifive-gpt.py b/util/riscv/sifive-gpt.py
new file mode 100755
index 0000000000..cb77302528
--- /dev/null
+++ b/util/riscv/sifive-gpt.py
@@ -0,0 +1,181 @@
+#!/usr/bin/python3
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2018 Jonathan Neuschäfer
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+import sys, os, struct, uuid, zlib, io
+
+# This script wraps the bootblock in a GPT partition, because that's what
+# SiFive's bootrom will load.
+
+
+# Size of a GPT disk block, in bytes
+BLOCK_SIZE = 512
+BLOCK_MASK = BLOCK_SIZE - 1
+
+# Size of the bootcode part of the MBR
+MBR_BOOTCODE_SIZE = 0x1be
+
+# A protecive MBR, without the bootcode part
+PROTECTIVE_MBR_FOOTER = bytes([
+    0x00, 0x00, 0x02, 0x00, 0xee, 0xff, 0xff, 0xff,
+    0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x55, 0xaa
+])
+
+
+# A "protective MBR"[1], which may also contain some boot code.
+# [1]: https://en.wikipedia.org/wiki/GUID_Partition_Table#PROTECTIVE-MBR
+class ProtectiveMBR:
+    def __init__(self):
+        self.bootcode = bytes(MBR_BOOTCODE_SIZE)
+
+    def generate(self, stream):
+        assert len(self.bootcode) == MBR_BOOTCODE_SIZE
+        mbr = self.bootcode + PROTECTIVE_MBR_FOOTER
+        assert len(mbr) == BLOCK_SIZE
+        stream.write(mbr)
+
+
+# Generate a GUID from a string
+class GUID(uuid.UUID):
+    def __init__(self, string):
+        super().__init__(string)
+
+    def get_bytes(self):
+        return self.bytes_le
+
+DUMMY_GUID_DISK_UNIQUE = GUID('17145242-abaa-441d-916a-3f26c970aba2')
+DUMMY_GUID_PART_UNIQUE = GUID('7552133d-c8de-4a20-924c-0e85f5ea81f2')
+GUID_TYPE_FSBL = GUID('5B193300-FC78-40CD-8002-E86C45580B47')
+
+
+# A GPT disk header
+# https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_table_header_(LBA_1)
+class GPTHeader:
+    def __init__(self):
+        self.current_lba = 1
+        self.backup_lba = 1
+        self.first_usable_lba = 2
+        self.last_usable_lba = 0xff     # dummy value
+        self.uniq = DUMMY_GUID_DISK_UNIQUE
+        self.part_entries_lba = 2
+        self.part_entries_number = 0
+        self.part_entries_crc32 = 0
+        self.part_entry_size = 128
+
+    def pack_with_crc(self, crc):
+        header_size = 92
+        header = struct.pack('<8sIIIIQQQQ16sQIII',
+                b'EFI PART', 0x100, header_size, crc, 0,
+                self.current_lba, self.backup_lba, self.first_usable_lba,
+                self.last_usable_lba, self.uniq.get_bytes(),
+                self.part_entries_lba, self.part_entries_number,
+                self.part_entry_size, self.part_entries_crc32)
+        assert len(header) == header_size
+        return header
+
+    def generate(self, stream):
+        crc = zlib.crc32(self.pack_with_crc(0))
+        header = self.pack_with_crc(crc)
+        stream.write(header.ljust(BLOCK_SIZE, b'\0'))
+
+
+# A GPT partition entry.
+# https://en.wikipedia.org/wiki/GUID_Partition_Table#Partition_entries_(LBA_2-33)
+class GPTPartition:
+    def __init__(self):
+        self.type = GUID('00000000-0000-0000-0000-000000000000')
+        self.uniq = GUID('00000000-0000-0000-0000-000000000000')
+        self.first_lba = 0
+        self.last_lba = 0
+        self.attr = 0
+        self.name = ''
+
+    def generate(self, stream):
+        name_utf16 = self.name.encode('UTF-16LE')
+        part = struct.pack('<16s16sQQQ72s',
+                self.type.get_bytes(), self.uniq.get_bytes(),
+                self.first_lba, self.last_lba, self.attr,
+                name_utf16.ljust(72, b'\0'))
+        assert len(part) == 128
+        stream.write(part)
+
+
+class GPTImage:
+    # The final image consists of:
+    # - A protective MBR
+    # - A GPT header
+    # - A few GPT partition entries
+    # - The content of the bootblock
+    def __init__(self):
+        self.mbr = ProtectiveMBR()
+        self.header = GPTHeader()
+        self.partitions = [ GPTPartition() for i in range(8) ]
+        self.bootblock = b''
+
+
+    # Fix up a few numbers to ensure consistency between the different
+    # components.
+    def fixup(self):
+        # Align the bootblock to a whole number to LBA blocks
+        bootblock_size = (len(self.bootblock) + BLOCK_SIZE - 1) & ~BLOCK_MASK
+        self.bootblock = self.bootblock.ljust(bootblock_size)
+
+        # Propagate the number of partition entries
+        self.header.part_entries_number = len(self.partitions)
+        self.header.first_usable_lba = 2 + self.header.part_entries_number // 4
+
+        # Create a partition entry for the bootblock
+        self.partitions[0].type = GUID_TYPE_FSBL
+        self.partitions[0].uniq = DUMMY_GUID_PART_UNIQUE
+        self.partitions[0].first_lba = self.header.first_usable_lba
+        self.partitions[0].last_lba = \
+            self.header.first_usable_lba + bootblock_size // BLOCK_SIZE
+
+        # Calculate the CRC32 checksum of the partitions array
+        partition_array = io.BytesIO()
+        for part in self.partitions:
+            part.generate(partition_array)
+        self.header.part_entries_crc32 = zlib.crc32(partition_array.getvalue())
+
+
+    def generate(self, stream):
+        self.mbr.generate(stream)
+        self.header.generate(stream)
+        for part in self.partitions:
+            part.generate(stream)
+        stream.write(self.bootblock)
+
+
+if __name__ == '__main__':
+    if len(sys.argv) != 3:
+        print('Usage:', file=sys.stderr)
+        print('    %s bootblock.raw.bin bootblock.bin' % sys.argv[0],
+                file=sys.stderr)
+        sys.exit(1)
+
+    image = GPTImage()
+
+    with open(sys.argv[1], 'rb') as f:
+        image.bootblock = f.read()
+
+    image.fixup()
+
+    with open(sys.argv[2], 'wb') as f:
+        image.generate(f)