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authorMarshall Dawson <marshalldawson3rd@gmail.com>2016-10-31 14:17:46 -0400
committerMartin Roth <martinroth@google.com>2016-11-07 20:37:21 +0100
commit6580408a7e0a19c68f9705884c1bcaf4638cc914 (patch)
tree94fddfd5bdb28cfa5e9328b46eac1859d0a5a696
parent21e5dd8a8503734e8f1199e5de0e3da1d84e3081 (diff)
downloadcoreboot-6580408a7e0a19c68f9705884c1bcaf4638cc914.tar.xz
amd/pi/hudson: Move audio to northbridge
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00) locate the HD audio controller on the northbridge root complex at 9.2 instead of the FCH. This duplicates the existing ASL into the northbridge directories and reports the correct address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438) Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17216 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/northbridge/amd/pi/00660F01/acpi/northbridge.asl37
-rw-r--r--src/northbridge/amd/pi/00670F00/acpi/northbridge.asl37
-rw-r--r--src/southbridge/amd/pi/hudson/acpi/fch.asl2
3 files changed, 76 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
index 022b347d29..d54f985e90 100644
--- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl
@@ -129,3 +129,40 @@ Device(PBRC) {
Return (PSC) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
+
+Device(AZHD) { /* 0:9.2 - HD Audio */
+ Name(_ADR, 0x00090002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method (_INI, 0, NotSerialized)
+ {
+ If (LEqual (OSVR, 0x03))
+ {
+ Store (Zero, NSEN)
+ Store (One, NSDO)
+ Store (One, NSDI)
+ }
+ }
+} /* end AZHD */
diff --git a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl
index e5cf34f07d..c5876ff4d4 100644
--- a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl
@@ -95,3 +95,40 @@ Device(PBR8) {
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */
+
+Device(AZHD) { /* 0:9.2 - HD Audio */
+ Name(_ADR, 0x00090002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method (_INI, 0, NotSerialized)
+ {
+ If (LEqual (OSVR, 0x03))
+ {
+ Store (Zero, NSEN)
+ Store (One, NSDO)
+ Store (One, NSDI)
+ }
+ }
+} /* end AZHD */
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 0426b00703..b8c0b35e88 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -51,7 +51,9 @@ Device(SBUS) {
#include "usb.asl"
/* 0:14.2 - HD Audio */
+#if !CONFIG_SOUTHBRIDGE_AMD_PI_KERN
#include "audio.asl"
+#endif
/* 0:14.3 - LPC */
#include "lpc.asl"