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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-13 16:19:23 +0200 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 19:21:25 +0100 |
| commit | 668828d3b3ffbe2891d6176379d990e99ae29be7 (patch) | |
| tree | 0bed1fbfdf2336f5176a4152f6c967f968437df0 | |
| parent | c5cd57c330694a63360be4d93ecf5cb23883aafc (diff) | |
| download | coreboot-668828d3b3ffbe2891d6176379d990e99ae29be7.tar.xz | |
siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry
Propagate commit d08057a change to this new FSP platform.
Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8662
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
| -rw-r--r-- | src/mainboard/siemens/mc_tcu3/irqroute.h | 38 |
1 files changed, 23 insertions, 15 deletions
diff --git a/src/mainboard/siemens/mc_tcu3/irqroute.h b/src/mainboard/siemens/mc_tcu3/irqroute.h index 08552c534c..bce6f63bb6 100644 --- a/src/mainboard/siemens/mc_tcu3/irqroute.h +++ b/src/mainboard/siemens/mc_tcu3/irqroute.h @@ -40,22 +40,30 @@ *IR1Eh SIO INT(ABCD) - PIRQ BDEF *IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* * Route each PIRQ[A-H] to a PIC IRQ[0-15] |