KBL: Update FSP headers - upgrade to FSP 2.5.0

 Additional UPDs included with FSP 2.5.0:
     FspsUpd.h:
       *SataRstOptaneMemory
       *Additional Upds for Core Ratio limit
     FspmUpd.h:
       *RingDownBin
       *PcdDebugInterfaceFlags
       *PcdSerialDebugBaudRate
       *PcdSerialDebugLevel
       *GtPllVoltageOffset
       *RingPllVoltageOffset
       *SaPllVoltageOffset
       *McPllVoltageOffset
       *RealtimeMemoryTiming
       *EvLoader
       *Avx3RatioOffset

CQ-DEPEND=CL:*388108,CL:*388109
BUG=None
BRANCH=None
TEST=Build and test on Soraka

Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: Id31ddd4595e36c91ba7c888688114c4dbe4db86a
Reviewed-on: https://review.coreboot.org/20123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 117 insertions, 16 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index dff96f0f4d..1916e4e1c0 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -840,7 +840,14 @@ typedef struct {
 /** Offset 0x02E2 - Core PLL voltage offset
   Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
 **/
-  UINT16                      CorePllVoltageOffset;
+  UINT8                       CorePllVoltageOffset;
+
+/** Offset 0x02E3 - Ring Downbin
+  Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+  lower than the core ratio.<b>0: Disable</b>; 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       RingDownBin;
 
 /** Offset 0x02E4 - BCLK Adaptive Voltage Enable
   When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
@@ -1154,11 +1161,11 @@ typedef struct {
 **/
   UINT32                      PcieRpEnableMask;
 
-/** Offset 0x050C - SerialIo Uart Debug
-  Enable SerialIo Uart debug.
-  0:Disable, 1:Enable
+/** Offset 0x050C - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
 **/
-  UINT8                       PcdSerialDebugEnable;
+  UINT8                       PcdDebugInterfaceFlags;
 
 /** Offset 0x050D - SerialIo Uart Number Selection
   Select SerialIo Uart Controller for debug.
@@ -1190,9 +1197,67 @@ typedef struct {
 **/
   UINT8                       PeciSxReset;
 
-/** Offset 0x0512
+/** Offset 0x0512 - PcdSerialDebugBaudRate
+  Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+  3:9600, 4:19200, 6:56700, 7:115200
+**/
+  UINT8                       PcdSerialDebugBaudRate;
+
+/** Offset 0x0513 - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x0514 - Enable or Disable EV Loader
+  Enable or Disable EV Loader; <b>0: Disable;</b> 1: Enable.
+  $EN_DIS
+**/
+  UINT8                       EvLoader;
+
+/** Offset 0x0515 - GT PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+  0x0:0xFF
+**/
+  UINT8                       GtPllVoltageOffset;
+
+/** Offset 0x0516 - Ring PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+  0x0:0xFF
+**/
+  UINT8                       RingPllVoltageOffset;
+
+/** Offset 0x0517 - System Agent PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+  0x0:0xFF
+**/
+  UINT8                       SaPllVoltageOffset;
+
+/** Offset 0x0518 - Memory Controller PLL voltage offset
+  Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+  0x0:0xFF
+**/
+  UINT8                       McPllVoltageOffset;
+
+/** Offset 0x0519 - Realtime Memory Timing
+  0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+  realtime memory timing changes after MRC_DONE.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       RealtimeMemoryTiming;
+
+/** Offset 0x051A - AVX3 Ratio Offset
+  0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+  vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+  UINT8                       Avx3RatioOffset;
+
+/** Offset 0x051B
 **/
-  UINT8                       ReservedFspmUpd[14];
+  UINT8                       ReservedFspmUpd[5];
 } FSP_M_CONFIG;
 
 /** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index e6ddbce116..e91bc796bf 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -221,7 +221,7 @@ typedef struct {
 **/
   UINT8                       XdciEnable;
 
-/** Offset 0x006D - Enable XHCI SSIC Eanble
+/** Offset 0x006D - Enable XHCI SSIC Enable
   Enable/disable XHCI SSIC port.
   $EN_DIS
 **/
@@ -1520,8 +1520,9 @@ typedef struct {
 **/
   UINT8                       UnusedUpdSpace18;
 
-/** Offset 0x065C - PCH Pm WOL_OVR_WK_STS
-  Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+/** Offset 0x065C - PCH Port 61h Config Enable/Disable
+  Used for the emulation feature for Port61h read. The port is trapped and the SMI
+  handler will toggle bit4 according to the handler's internal state.
   $EN_DIS
 **/
   UINT8                       PchPort61hEnable;
@@ -1959,9 +1960,15 @@ typedef struct {
 **/
   UINT8                       Early8254ClockGatingEnable;
 
-/** Offset 0x0720
+/** Offset 0x0720 - PCH Sata Rst Optane Memory
+  Optane Memory
+  $EN_DIS
+**/
+  UINT8                       SataRstOptaneMemory;
+
+/** Offset 0x0721
 **/
-  UINT8                       UnusedUpdSpace19[4];
+  UINT8                       UnusedUpdSpace19[3];
 
 /** Offset 0x0724 - Pch PCIE device override table pointer
   The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -2065,7 +2072,7 @@ typedef struct {
 **/
   UINT8                       ChapDeviceEnable;
 
-/** Offset 0x0785 - Skip PAM regsiter lock
+/** Offset 0x0785 - Skip PAM register lock
   Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
   PAM registers will be locked by RC
   $EN_DIS
@@ -2145,7 +2152,8 @@ typedef struct {
 /** Offset 0x079C - 1-Core Ratio Limit
   1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
   1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
-  to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
+  to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,
+  6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83
 **/
   UINT8                       OneCoreRatioLimit;
 
@@ -2740,11 +2748,39 @@ typedef struct {
 **/
   UINT32                      CpuS3ResumeData;
 
-/** Offset 0x0884 - ReservedCpuPostMemTest
+/** Offset 0x0884 - 5-Core Ratio Limit
+  5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+  5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
+  to 1-Core Ratio Limit.Range is 0 to 83
+**/
+  UINT8                       FiveCoreRatioLimit;
+
+/** Offset 0x0885 - 6-Core Ratio Limit
+  6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+  6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
+  to 1-Core Ratio Limit.Range is 0 to 83
+**/
+  UINT8                       SixCoreRatioLimit;
+
+/** Offset 0x0886 - 7-Core Ratio Limit
+  7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+  7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
+  to 1-Core Ratio Limit.Range is 0 to 83
+**/
+  UINT8                       SevenCoreRatioLimit;
+
+/** Offset 0x0887 - 8-Core Ratio Limit
+  8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+  8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
+  to 1-Core Ratio Limit.Range is 0 to 83
+**/
+  UINT8                       EightCoreRatioLimit;
+
+/** Offset 0x0888 - ReservedCpuPostMemTest
   Reserved for CPU Post-Mem Test
   $EN_DIS
 **/
-  UINT8                       ReservedCpuPostMemTest[6];
+  UINT8                       ReservedCpuPostMemTest[2];
 
 /** Offset 0x088A - SgxSinitDataFromTpm
   SgxSinitDataFromTpm default values