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authorMartin Roth <martinroth@google.com>2018-06-07 09:00:22 -0600
committerMartin Roth <martinroth@google.com>2018-06-08 16:12:54 +0000
commit6985a7b7d6367b4aae3f5c03290f19feea7580f0 (patch)
tree802693690e10448d9067a8760fcd73af3964f00f
parent82e8c69a56dbb9d16631a77b7971977800913af7 (diff)
downloadcoreboot-6985a7b7d6367b4aae3f5c03290f19feea7580f0.tar.xz
mainboard/google/kahlee: Use 66MHz SPI clock for fast read
Looking at the 100MHz signal, we were violating the timing requirements. 66MHz still isn't great, but it's a good tradeoff between improving the signal and losing boot speed time. This slows down the boot time by about 20mS. BUG=b:109583457 TEST=Boot grunt, look at signal on scope Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
-rw-r--r--src/mainboard/google/kahlee/bootblock/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 8f124b36ff..7e6524d1d5 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -44,7 +44,7 @@ void bootblock_mainboard_init(void)
/* Set SPI speeds before verstage. Needed for TPM */
sb_set_spi100(SPI_SPEED_33M, /* Normal */
- SPI_SPEED_100M, /* Fast */
+ SPI_SPEED_66M, /* Fast */
SPI_SPEED_66M, /* AltIO */
SPI_SPEED_66M); /* TPM */