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authorNick Vaccaro <nvaccaro@google.com>2018-10-01 17:15:12 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-10-04 09:45:35 +0000
commit6a7f5845e7a83eff20b3663784f4029ea9f34c52 (patch)
treec223ef0655dadb262775cb1e3863c7461a208364
parent8b6f8cc1aca3a80068d1013c6b7c316fec16cbd2 (diff)
downloadcoreboot-6a7f5845e7a83eff20b3663784f4029ea9f34c52.tar.xz
mb/google/poppy/variant/nocturne: update GPIO configuration
GPP_C19 is not being set as the code is incorrectly setting GPP_C16 instead, causing SAR sensor not to work, so this change sets GPP_C19 to NF1. GPP_E3 is not being initialized in the code. Initialize GPP_E3 to a no connect as documented in the board schematic. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28867 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/gpio.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 99b2dcf51b..8f87705073 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -151,7 +151,7 @@ static const struct pad_config gpio_table[] = {
/* C18 : I2C1_SDA ==> PCH_I2C1_DISPLAY_SAR_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_DISPLAY_SAR_SCL */
- PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
@@ -217,6 +217,8 @@ static const struct pad_config gpio_table[] = {
/* E2 : SATAXPCIE2 ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_E2, 1, DEEP),
/* E3 : CPU_GP0 ==> NC */
+ PAD_CFG_NC(GPP_E3),
+ /* E3 : DEVSLP0 ==> NC */
PAD_CFG_NC(GPP_E4),
/* E5 : SATA_DEVSLP1 ==> NC */
PAD_CFG_NC(GPP_E5),